Impedence buffering MOS circuit with dynamically reduced thresho

Details Impedence buffering MOS circuit with dynamically reduced thresho Impedence buffering MOS circuit with dynamically reduced thresho

1994-03-28

1996-09-24

Kuntz, Curtis

Electrical audio signal processing systems and devices

Sound effects

Reverberators

381 682, 327312, 327379, 327434, 327437, 330277, 330307, H04R 2500, H03F 316

Patent

active

055598927

ABSTRACT:
A buffer circuit, such as for use with a low voltage hearing aid, is disclosed. The hearing aid comprises a microphone, a receiver and an amplifier. The amplifier is disposed between the microphone and the receiver. The buffer circuit has a MOS device including a well terminal and a gate terminal equipotentially coupled together to reduce the effective threshold voltage of the MOS device, thereby reducing the gate-to-source voltage of the MOS device. This permits a greater linear output signal range for the amplifier.

REFERENCES:
patent: 3823332 (1974-07-01), Feryszka et al.
patent: 4495384 (1985-01-01), Scott et al.
patent: 4509193 (1985-04-01), Carlson
patent: 4539441 (1985-09-01), Eggert et al.
patent: 5097515 (1992-03-01), Baba
patent: 5105102 (1994-04-01), Shioda
patent: 5194831 (1993-03-01), Jackson
patent: 5208867 (1993-05-01), Stites, III
RCA COS/MOS Integrated Circuit Manual, 1971 RCA Corp. pp. 134-137.

Affiliated with

Also associated with

Rating

Impedence buffering MOS circuit with dynamically reduced thresho does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Impedence buffering MOS circuit with dynamically reduced thresho, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Impedence buffering MOS circuit with dynamically reduced thresho will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1946722