Impedance tuning circuit

Details Impedance tuning circuit Impedance tuning circuit

2002-06-25

2004-06-22

Cunningham, Terry D. (Department: 2816)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

C331S167000, C331S17700V, C331S1170FE, C331S17700V

Reexamination Certificate

active

06753738

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to feedback control systems, and particularly to those feedback systems utilizing phase-locked loops.
Feedback systems are well known in the art and are found in a multitude of different configurations. One such well-known configuration is a phase locked loop (PLL). A generalized block diagram is shown in
FIG. 1
of a traditional PLL configured for a clock and data recovery application. Such a configuration may be used for recovering clock and data streams compatible with the SONET specification, as well as others. The phase locked loop
100
includes a phase detector
102
(or alternatively, a phase/frequency detector) which receives the input data signal conveyed on node
112
and receives a data clock signal conveyed on node
122
. The phase detector
102
generates on its output node
116
an error signal which is a function of the phase difference (and frequency difference in the case of a phase/frequency detector) between the input data signal and the data clock signal, and often includes data retiming circuitry to generate on an output node
114
the reconstructed data, as shown.
A loop filter
104
filters the output of the phase detector
102
to generate a control voltage signal on node
118
which is provided to a voltage controlled oscillator
110
in order to influence the frequency (and hence the phase) of the VCO output clock signal conveyed on node
120
. The loop filter
104
frequently includes an integrator block which is implemented using a charge pump and a loop filter capacitor. The VCO output clock signal may be divided-down by divider
106
to generate the data clock signal (conveyed on node
122
) based upon the expected data rate of the incoming data signal.
If such a PLL were implemented using discrete components, precision components could be used to provide a nominal VCO frequency relatively close to a desired center frequency. However, such a discrete implementation is costly and requires a large amount of printed wiring board space, and more than likely would have difficulty achieving the performance required of modem systems while operating at an acceptable power level. Consequently, most VCOs are implemented monolithicly (i.e., on a single integrated circuit die). As is well known in the art, the absolute value of certain parameters on an integrated circuit may vary greatly due to process variations (e.g., lot-to-lot variations, wafer-to-wafer variations within a lot, die-to-die variations within a wafer) and as environmental variables change (e.g., die temperature, power supply voltage variations, etc.). Even though the tracking of certain parameters within a single integrated circuit is frequently quite good (which is the basis of many advantageous circuit techniques), the nominal frequency of many VCO circuits can vary greatly from die to die. While the frequency of the VCO can inherently be adjusted by an appropriate control voltage, the subsequent adjustability of the VCO may be reduced if the control voltage otherwise necessary to achieve the initially-desired VCO frequency falls too close to either the upper extreme or the lower extreme of its range. Said differently, such a PLL
100
may perform more optimally over time when the control voltage for the VCO is nominally somewhat centered within its expected voltage range.
One possible technique increases the gain of the VCO so that large changes in VCO frequency may be achieved by changes in the control voltage well within the expected range of control voltages. In principle this would allow a PLL to compensate for a large deviation in VCO “center frequency” without requiring a control voltage dangerously close to “running out of range.” But there are detrimental consequences of increasing the VCO gain, including danger of locking onto a harmonic, and increased noise and jitter of the system. Moreover, with most VCO circuit structures it is difficult to arbitrarily provide an ever higher and higher tuning range and still achieve good frequency and phase stability.
One approach to accommodating the VCO center frequency variations involves trimming the frequency using, for example, a precision laser. After the semiconductor fabrication steps are complete, and either during wafer-level testing or possibly after singulization of individual circuit dies, the VCO is tested to determine its center frequency, and various circuit elements (e.g., resistors, capacitors) are trimmed to adjust the center frequency to the desired value. The remaining testing and packaging operations are then performed to complete the manufacturing of the circuits. Alternatively, such trimming may also be accomplished using a flash memory programming technique coupled with appropriate selection circuits, although this requires a semiconductor process capable of forming compatible flash memory elements. In either case, such trimming is a “permanent” adjustment of the center frequency during manufacture, but it adds costly manufacturing steps to either accomplish laser trimming after wafer fabrication or to provide a semiconductor process capable of implementing flash memory structures or other kinds of programmable structures. Moreover, such trimming is performed once during manufacture, and cannot adjust for subsequent changes in environmental conditions that the circuit may be called upon to operate under.
Another approach to accommodating the VCO center frequency variations involves calibrating the VCO center frequency each time the circuit is powered-up. Such techniques may involve comparing the center frequency against an externally provided reference frequency signal and setting a number of storage elements (e.g., registers) to appropriately adjust the center frequency. Such storage elements are volatile and lose stored data when the circuit loses power. An example of a device that performs such a calibration upon power-up is the Si4133G RF Synthesizer, which is available from Silicon Laboratories, Inc. based in Austin, Tex.
These approaches are valuable additions to the state of the art, but they cannot accommodate variations in the center frequency as environmental conditions change, as semiconductor parameters drift over time (e.g., threshold voltage shifts), or as other artifacts of component aging occur. This becomes increasingly more important in certain industrial systems which are put into operation and virtually never shut down. Examples include various interface circuits within the telecommunications infrastructure, which may operate for years without an opportunity to recalibrate during a subsequent power-up operation.
What is needed is an effective way to accommodate environmental or parametric changes in a feedback system which occur after the system is powered up and while operational, without negatively impacting the operation of the feedback system within its intended specifications.
SUMMARY OF THE INVENTION
Such a capability may be accomplished in a clock and data recovery circuit, such as PLL
100
, by introducing a second feedback loop which reacts to the control voltage reaching a level sufficiently different from its mid-range value by slowly adjusting additional tuning elements which, along with the tuning elements controlled by the control voltage signal, control the VCO frequency. Absent the first traditional feedback loop, a change in the VCO frequency would result, but the second feedback loop is arranged to cause a slow enough change in the VCO frequency that the first feedback loop is able to compensate for the would-be change by adjusting the control voltage quickly enough in a direction toward the mid-range value to keep the VCO frequency substantially unchanged. The second feedback loop may advantageously incorporate one or more digital control signals to affect a tuning change by changing from one state to another state. These digital signals preferably change no more than one bit at a time, and the single bit which changes is preferably caused to achieve a controlled transition time (or ramp rate) which is slow enough to c

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