Impedance-matched write circuit with shunted matching resistor

Details Impedance-matched write circuit with shunted matching resistor Impedance-matched write circuit with shunted matching resistor

2004-02-11

2008-12-16

Negrón, Daniell L (Department: 2627)

Dynamic magnetic information storage or retrieval

General recording or reproducing

Specifics of the amplifier

Reexamination Certificate

active

07466508

ABSTRACT:
An impedance matched write circuit is provided that shunts one or more matching resistors. The impedance matched write circuit includes an interconnect for connecting to a write head and at least one resistor between a control voltage and the interconnect for impedance matching to the interconnect. A transistor can be connected across the resistor to shunt current that would otherwise pass through the resistor during an overshoot mode. The transistor may be a PMOS transistor or a combination of PMOS and NMOS transistors. A gate voltage of the transistor is controlled by a source such that the transistor is turned on in an overshoot mode and turned off during a steady state mode.

REFERENCES:
patent: 6121800 (2000-09-01), Leighton et al.
patent: 6184727 (2001-02-01), Price, Jr.
patent: 6236247 (2001-05-01), Ngo
patent: 6512646 (2003-01-01), Leighton et al.

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