Impedance-matched write circuit

Details Impedance-matched write circuit Impedance-matched write circuit

1999-12-30

2003-01-28

Hudspeth, David (Department: 2651)

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Head amplifier circuit

C360S068000, C327S110000

Reexamination Certificate

active

06512646

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to drivers for write heads of magnetic disk drives, and particularly to write drivers having impedance matching characteristics.
Rigid magnetic disk drives employ E-block assemblies supporting a plurality of actuator arms each having a read head and a write head at the distal end thereof and arranged to move with the E-block across the radius of the magnetic recording disk. The writer circuit, or write driver, is included in an integrated circuit chip mounted on the E-block at the proximal end of the actuator arms and is connected to the write heads at the distal end through interconnect cable. Typically, the interconnect exhibits 100 Ohms differential impedance (Zdiff), 30 Ohms common-mode impedance (Zcm) and 250 picoseconds propagation delay time (&tgr;). The write head typically exhibits 25 nano-Henries of inductance (L) in parallel with 200 Ohms parallel resistance (R
P
) with a series resistance of 10 Ohms (R
S
) in series with the parallel L-R
P
circuit.
A typical write circuit generates a square wave current pattern through the write head, with each current pulse being composed of a rise-time portion, an overshoot portion, and a steady-state portion. The overshoot portion represents the portion of the pulse where the absolute value of the current exceeds the absolute value of the steady-state current; for example, where the steady state current is 40 mA, the overshoot current may reach a peak of 70 mA. The rise-time is defined as the time that it takes the current to change from 10% to 90% of its steady-state current, as it swings from one direction to the other. Thus, for a writer programmed for 40 mA steady-state write current, the rise time is defined as the time required for the current in the write head to change from −32 MA to +32 mA, and vice versa.
There have been many improvements to conventional write circuits to enhance their performance. However, these improved current-switching write circuits still are unable to achieve impedance matching to the interconnect, since such impedance matching would require a small resistor in parallel with the write head which would shunt the write current away from the write head during operation of the circuit and thereby render the circuit inoperable. The lack of impedance matching results in pattern dependent distortion which limits the performance of the write circuit. It would therefore be beneficial to the state of the art to provide a write circuit that operates on a principle that is somewhat different than that of conventional write circuits, so that the circuit can be impedance matched to the interconnect and thereby reduce or eliminate pattern dependent distortion while providing excellent performance.
BRIEF SUMMARY OF THE INVENTION
The present invention is an impedance-matched write circuit that selectively provides a write current through a write head in first and second opposite directions. The write circuit is connected to the write head by an interconnect, and has a positive supply level and a negative supply level. A first voltage source provides a first control voltage, and a second voltage source provides a second control voltage. A first resistor is provided between the first voltage source and the interconnect for impedance matching to the interconnect, and a second resistor is provided between the second voltage source and the interconnect for impedance matching to the interconnect. The first and second control voltages provide a transient voltage to the interconnect and provide a subsequent steady-state voltage to the interconnect. In one embodiment, first and second current sinks are provided to sink a first current from a first side of the interconnect when a first voltage at the first side of the interconnect is low; and to sink a second current from a second side opposite the first side of the interconnect when a second voltage at the second side of the interconnect is low, thereby increasing the transient voltage delivered to the interconnect.


REFERENCES:
patent: 5869988 (1999-02-01), Jusuf et al.
patent: 6121800 (2000-09-01), Leighton et al.
patent: WO 98/10420 (1998-03-01), None
patent: WO 99/60562 (1999-11-01), None

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