Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2000-06-07
2001-06-05
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S233100, C365S230030
Reexamination Certificate
active
06243283
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to computer systems and memory system architectures, and specifically, to a method and apparatus for controlling device impedance loading in semiconductor circuits and device structures by implementing and selectively destructing novel fuse devices in the semiconductor chips.
2. Discussion of the Prior Art
Processor performance is increasingly gated by memory performance. Cache hierarchies are used to accommodate fast processors and fast memories. However, as processor speeds dramatically increase, provision of cache memories becomes increasingly insufficient, primarily due to input capacitance loading which is a major limiting factor. For example, memory chip devices are provisioned with protective devices which are used to protect the device from electrostatic discharge, for example, during device manufacture and handling. These protective devices can increase input capacitance by as much as 25%. For example, in a memory device having a common input/output terminal, a combined receiver and output driver may have a capacitance of 24 pf, with the protective device adding an additional 6 pf.
Furthermore, to enhance latency, it is necessary to reduce delay time, deleterious transmission line effects (‘ringing’), loading, etc. Not only is the reduction of chip and package parasitic capacitance and inductance necessary for high performance operation, but the physical proximity between processors/memory controllers and memories is also a key to achieving reduced latency. High bandwidth (high clock rates) require terminated lines, reduced loads, etc.
It would be highly desirable to provide an apparatus and method for eliminating the protective devices of logic and memory chips/devices in the final assembly so that memory and processor performance may be enhanced without increasing electrostatic charge sensitivity of the logic or memory chip/device.
It would additionally be desirable to provide an apparatus and method for eliminating the protective devices of memory chips/chips by implementing a novel fuse structure in the protective device that may be blown after final packaging in order to eliminate loading of the protective device.
Furthermore, it would be desirable to more tightly/closely couple memory and processor chips, by providing a novel stacked memory chip/device structure that eliminates excessive capacitive and inductive loading in single and multi-processor systems in order to achieve lower latency and higher-bandwidth operation.
Finally, as prior art laser fuse devices must be blown at the wafer level prior to packaging and module burn-in, stresses may be introduced onto the chip that can promote circuit fails and performance anomalies. Laser fuses cannot be blown after circuit encapsulation and, therefore, cannot be used to correct circuit problems introduced during final module build. Thus, it would be highly desirable to provide a novel electrical fuse device, that enables circuit binning and repair to be accomplished after chip encapsulation which serves to enhance over all product yield.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a novel electronic fuse structure for integrated circuits that is fabricated for connection between a protective device and active circuitry that is connected to an I/O pad of the semi-conductor chip circuit, and that may be blown after final assembly for disconnecting the protective device and reducing load impedance at the I/O pad connection.
It is another object of the present invention to provide an apparatus and method for reducing load impedance at an input or I/O pad connection of an integrated semi-conductor chip circuit that requires blowing of a novel electronic fuse structure for disconnecting one or more off-chip driver (OCD) circuits connected between the input or I/O pad and active chip circuitry.
It is a further object of the invention to more tightly/closely couple memory and processor chips, by providing a novel stacked memory chip/device structure that eliminates excessive capacitive and inductive loading in single and multi-processor systems in order to achieve lower latency and higher-bandwidth operation.
Yet another object of the present invention is to provide a novel electronic fuse structure for integrated circuits that may be blown for accomplishing circuit binning and repair after chip encapsulation.
According to a first aspect of the invention, there is provided a system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective device; connecting a current source device associated with each fuse device in the integrated circuit, the current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the current source and the I/O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I/O connection.
Advantageously, the invention is well suited for implementation in DRAM, SRAM, logic and other circuits that may require the blowing of over a thousand lines, for example, during manufacture.
According to a further aspect of the invention, there is provided a system comprising integrated circuit chips disposed in a stacked relation, each chip comprising: a layer of active circuitry formed at a first layer of each chip; a plurality of through conducting structures disposed substantially vertically through each chip for enabling electronic connection with active circuitry at the first layer; second conducting means disposed at an end of the through conducting means at an opposite side of a chip for connection with a corresponding through conductive means of an adjacent stacked chip, the stacked chip structure formed by aligning one or more through conducting structures and second conducting means of adjacent chips, whereby a chip of the stack is electronically connected to active circuitry formed on other chips of the stack. Advantageously, the stacked chip structure is ideal for reducing data access latency in memory systems employing memory chips such as DRAM.
REFERENCES:
patent: 5432729 (1995-07-01), Carson et al.
patent: 5581498 (1996-12-01), Ludwig et al.
Bertin Claude Louis
Fifield John A.
Hedberg Erik Leigh
Houghton Russell J.
Sullivan Timothy Dooling
International Business Machines - Corporation
Le Vu A.
Scully Scott Murphy & Presser
Walter, Jr. Esq. Howard J.
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