Impedance control circuit for an integrated circuit node

Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock

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Details

307542, 307549, 307567, H03K 1716

Patent

active

050557114

ABSTRACT:
The present disclosure is of a novel circuit for controlling the impedance of an integrated circuit node during power-off and transient power conditions. The circuit includes a PNP transistor having an emitter-collector circuit connected between the circuit node and a ground node. The base of the transistor is connected to the ground node by a resistance, which holds the voltage at the base of the PNP transistor near ground potential when a signal is applied to the circuit node. The resistance can be implemented with a pinch resistor or as a FET transistor. The emitter of the PNP transistor clamps the voltage at the node to a value equal to the voltage drop across the resistor plus the forward voltage drop across the emitter-base circuit of the PNP transistor, the sum of which is less than the minimally necessary base-emitter turn-on voltage of a Darlington-connected NPN transistor pair. The forward voltage drop across the emitter-base circuit of the PNP decreases with increasing temperature, thereby reducing the clamp voltage to compensate for the temperature coefficients of the base-emitter junctions of the NPN transistors. When power is applied to the integrated circuit, a current source connected to the base of the PNP transistor generates a current to reverse-bias the emitter-base circuit of the PNP transistor, effectively disconnecting the PNP transistor from the circuit node.

REFERENCES:
patent: 3654530 (1972-04-01), Lloyd
patent: 4289977 (1981-09-01), Powers et al.
patent: 4525637 (1985-06-01), Sano et al.
patent: 4678950 (1987-07-01), Mitake
patent: 4777387 (1988-10-01), Collins
A. B. Grebene, Bipolar and MOS Analog Integrated Circuit Design, 1984, pp. 135-155.

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