Impedance-compensating circuit

Wave transmission lines and networks – Dissipating terminations for long lines – Fluid-cooling

Reexamination Certificate

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Details

C333S032000

Reexamination Certificate

active

06600384

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
The present invention relates to circuits providing impedance compensation over a frequency range, and in particular, a circuit having a pair of impedance circuits connected between first and second circuit terminals, each impedance circuit having resistance and frequency-responsive components. In its preferred form, the invention relates to terminations for transmission lines having a conventional termination and compensation for the conventional termination.
At radio frequencies, uniform transmission lines, such as microstrip lines and coplanar transmission lines, exhibit a characteristic impedance. Line terminations are used in certain circuits, such as directional couplers. A termination is provided by applying a resistive load at the end of the line, which load is equal in magnitude to the magnitude of the characteristic impedance. This is usually in the form of a thin film deposited resistor made on an insulating substrate on which a signal conductor of the line is formed. The resistive load couples the end of the signal conductor to a ground conductor.
The resistive load, when connected to ground, has a reactance component. Typically this reactance component is predominantly inductive at radio frequencies. This results in an impedance mismatch between the transmission line and the resistive load termination. It is known to compensate for the inductive reactance component by adding shunt capacitance to the resistive load, as disclosed in U.S. Pat. No. 4,413,241. Such a design provides a reasonably well-matched termination at a design frequency although the resistance of the termination is increased with the addition of the capacitance. However, for frequencies varying from the design frequency, it is desirable to have a termination having a real part that is equal to the characteristic impedance of a line being terminated and having a very low reactive component.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to a circuit that provides impedance compensation and, in its preferred form, provides compensated impedance for broadband applications. It includes a first impedance circuit having a first resistance device connected to a first impedance device. A second impedance circuit includes a second resistance device connected to a second impedance device. The first and second impedance circuits couple first and second circuit terminals. The product of the impedances of the first and second impedance devices is preferably substantially equal to the product of the resistances of the first and second resistance devices.
As used herein, an impedance circuit or device is any circuit component or circuit of components that provide impedance to a signal. Typical examples of circuit components include resistors, capacitors and inductors, but may also include other devices, such as transmission lines, stubs, vias, and active devices that add resistance, capacitance or inductance to the circuit. Such components may provide a combination of impedance types, such as inductance and resistance, and are typically distributed impedances at high frequencies. An impedance of a circuit element is considered to be distributed when it exists along a dimension of the circuit element, such as inductance along the length of a transmission line.
In the preferred embodiment, the invention provides a termination circuit for a microstrip transmission line including a strip signal conductor on the first face of a substrate and a ground plane on the second face of the substrate. A first termination or load resistor is coupled to ground through a short-circuit transmission line in the form of a via. The via extends through the substrate between the first face of the substrate and the ground plane. An open-circuit stub is formed on the first face of the substrate to compensate for the via. A second resistor couples the end of the signal conductor to the open-circuit stub. The first and second resistors are each equal to the characteristic impedance of the line. As will be seen, the product of the impedances of the open-circuit stub and the via is substantially equal to the square of the resistances of the first and second resistors.
The open-circuit stub exhibits primarily a capacitive impedance in the series circuit with the second resistor. The stub thus compensates for the parasitic inductance due to the line length of the via, particularly at higher frequencies.
Further, at a known frequency, the magnitude of the impedance of the stub is preferably set to be equal to the magnitude of the impedance of the via, which impedances are also equal to the values of the resistors. At lower frequencies the capacitive impedance of the stub increases and the inductive impedance of the via decreases. The reverse is true for higher frequencies. The total impedance for the combined termination thus stays relatively constant and real (resistive) over a wide frequency range.
A termination according to the invention is particularly useful in a directional coupler, such as is used in a balanced amplifier.
In a modified version of the invention, the first resistance device is connected in parallel with the second impedance device, and the second resistance device is connected in parallel with the first impedance device. This embodiment is particularly useful in applications in which a terminated device exhibits high impedance.
These and other features and advantages of the present invention will be apparent from the preferred embodiment described in the following detailed description and illustrated in the accompanying drawings.


REFERENCES:
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patent: 3895435 (1975-07-01), Turner et al.
patent: 4413241 (1983-11-01), Bitoune et al.
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patent: 5424693 (1995-06-01), Lin
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patent: 5768109 (1998-06-01), Gulick et al.
patent: 6198362 (2001-03-01), Harada et al.
Pearson, S.I. and Maler, G.J.,Introductory Circuit Analysis, (John Wiley & Sons, Inc., New York) 1965, pp. 490-497.
Van Valkenburg, M. E.,Network Analysis, third Edition, (Prentice-Hall, Englewood Cliffs, New Jersey) 1955, pp. 81-82.
Arai, Y., Sato, M., Yamada, H. T., Hamada, T., Nagaik., and Fujishiro, H. I., “60GHz Flip-Chip Assembled MIC Design Considering Chip-Substrate Effect”,IEEE MTT-S Digest, pp. 447-450, 1997.

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