Immediate floating-point operand reformatting in a microprocesso

Details Immediate floating-point operand reformatting in a microprocesso Immediate floating-point operand reformatting in a microprocesso

1997-04-30

1999-08-17

Ngo, Chuong Dinh

Boots, shoes, and leggings

36474801, G06F 738

Patent

active

059403110

ABSTRACT:
A microprocessor (5) having an on-chip floating-point unit, or FPU, (31) is disclosed. Snoop logic (37) is present in the integer pipeline to detect the presence of floating-point load instructions, in which floating-point operands are retrieved from system main memory or from on-chip cache memory (6, 16.sub.d, 18) by load/store units 40. For such operations in which the floating-point operands are of single precision or double precision, immediate formatter (70) receives the retrieved operands on load/store buses (LOAD.sub.-- DATA0, LOAD.sub.-- DATA1) and reformats the operands into a higher precision format for use internally by FPU (31). Rebias circuitry (78) is provided within immediate formatter (70) to change the bias of the exponent portion of the reformatted floating-point operands. Selection of the appropriate operand for application to the execution stages (56, 58, 60) of FPU (31) is made by a multiplexer (74) responsive to control signals (BSEL) derived from load/store directives detected by snoop logic (37). The operation of the immediate formatter (70) enables the reformatting of single precision and double precision floating-point operands within the same machine cycle as their receipt on load/store buses (LOAD.sub.-- DATA0, LOAD.sub.-- DATA1), thus improving performance of microprocessor (5).

REFERENCES:
patent: 4949291 (1990-08-01), Saini
patent: 5523961 (1996-06-01), Naini
patent: 5687106 (1997-11-01), Schwarz et al.

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