Imbalance circuits for DC testing

Details Imbalance circuits for DC testing Imbalance circuits for DC testing

1983-07-25

1986-08-05

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307565, H03K 1920, H03K 508

Patent

active

046045317

ABSTRACT:
This teaches that logic circuits such as Cascode circuits can be D.C. tested for normally untestable defects, such as emitter shorts or collector opens, by applying to the output of the circuit, or portion of the circuit, under test an additional voltage though an impedance. The specific embodiment teaches a resistor and diode in series as the impedence.

REFERENCES:
patent: 2964652 (1960-12-01), Yourke
patent: 3505535 (1970-04-01), Cavaliere
patent: 3541441 (1970-11-01), Hrustich
patent: 3795859 (1974-03-01), Benante et al.
patent: 4041326 (1977-08-01), Robinson
IBM Tech. Disclosure Bulletin, Programmable Swing Current Switch for Low-Power High Speed Circuits, H. D. Varadrajan, vol. 19, No. 10, Mar. 1977, p. 3736.
IBM Technical Disclosure Bulletin, vol. 21, No. 8, Jan. 1979, pp. 3107-3108 entitled "Sense Signal Characterization and Test for One-Device Dynamic Memory".

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