Imaging and graphics processing system

Details Imaging and graphics processing system Imaging and graphics processing system

1993-08-02

1995-11-14

Elmore, Reba I.

Boots, shoes, and leggings

39549704, 395412, 364DIG1, 3642463, 3642558, 3649403, 364DIG2, 3649664, G06F 1204, G06F 1300

Patent

active

054674590

ABSTRACT:
The present invention provides a unified image and graphics processing system that provides both image and graphics processing at high speeds. The system includes a parallel vector processing unit, a graphics subsystem, a shared memory and a set of high-speed data buses for connecting all of the other components. Generally, the parallel vector processing unit includes a series of vector processors. Each processor includes a vector address generator for efficient generation of memory addresses for regular address sequences. In order to synchronize and control the vector processors' accesses to shared memory, the parallel vector processing unit includes shared memory access logic. The logic is incorporated into each vector processor. The graphics subsystem includes a series of polygon processors in a pipelined configuration. Each processor is connected in the pipeline by a first-in-first-out (FIFO) buffer for passing data results. Additionally, each polygon processor is connected to a local shared memory in which program instructions and data are stored. The graphics subsystem also includes a device addressing mechanism for identifying a destination device using a tagged address. The shared memory, the parallel vector processor and the graphics subsystem also incorporate an abbreviated addressing scheme, which reduces the amount of information required to request sequential addresses from the shared memory.

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Akira Fujimoto, "A 3-D Graphics Display System With Depth Buffer and Pipeline Processor," IEEE Computer Graphics and Applications, Jun. 1984, pp. 49-61.

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