Image suppression filter circuit

Details Image suppression filter circuit Image suppression filter circuit

2006-01-24

2006-01-24

Hong, Harry S. (Department: 2642)

Telecommunications

Receiver or analog modulated signal frequency converter

Noise or interference elimination

C455S114200, C455S323000

Reexamination Certificate

active

06990326

ABSTRACT:
An image suppression filter circuit comprises a first phase shifter outputting a first output signal and a second output signal substantially orthogonal thereto, a second phase shifter outputting a third output signal and a fourth output signal orthogonal to the third output signal, a first subtracter subtracting the fourth output signal from the first output signal, a first adder adding the second and third output signals, a third phase shifter outputting a fifth output signal and a sixth output signal orthogonal to the fifth output signal, a fourth phase shifter outputting a seventh output signal and an eighth output signal orthogonal thereto, a second subtracter subtracting the eighth output signal from the fifth output signal, and a second adder adding the sixth and the seventh output signals.

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Jan Crols, et al., “A Single-Chip 900 MHz CMOS Receiver Front-End with a High Performance Low-IF Topology”, IEEE Journal of Solid-State Circuits, vol. 30, No. 12, pp. 1483-1492, Dec. 1995.

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