Facsimile and static presentation processing – Static presentation processing – Communication
Reexamination Certificate
1998-10-06
2002-06-25
Nguyen, Madeleine (Department: 2622)
Facsimile and static presentation processing
Static presentation processing
Communication
C358S426010
Reexamination Certificate
active
06411394
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an image signal processing apparatus for encoding an image signal into a code signal and decoding a code signal into an image signal at a high speed. More particularly, the invention relates to an image signal processing apparatus and an information transmission and reception apparatus for encoding a bit map image signal into a code signal and decoding a code signal into an image signal at a high speed.
In a facsimile apparatus for transmitting white-and-black binary image data, MH, MR, MMR encoding schemes are used to improve the transmission efficiency as recommended by CCITT (Consultative Committee in International Telegraphy and Telephony). Apparatuses of this type are, for example, M66330SP/FP disclosed in Mitsubishi Semiconductor Data Book and HD63185FS (DICEP-E) disclosed in the User Manual published by the semiconductor department of Hitachi Ltd.
If the number of transition points per unit length is large, the encoding speed lowers and the amount of encoded codes increases. When the number of transition points per unit length exceeds a certain limit, the amount of encoded codes exceeds the number of image data bits. A technique of reducing the amount of encoded codes is disclosed in JP-A-61-252765.
High speed image signal decoding systems for decoding an encoded image signal into an original image signal at a high speed are known as in the following.
In a “plain paper laser facsimile” described in the magazine Denshi Gijutsu,1990-8, a decoded image signal is stored in a page memory having a capacity of more than one page, and the stored image signal is outputted at a constant high speed to a laser printer.
In the Publication JP-A-59-126368, an encoded signal supplied via a system bus is decoded by accessing an image signal on a reference line stored in an image memory connected to an image bus. The decoded image signal is stored in the image memory and outputted to a printer.
In the article “Introduction of ASIC to High Speed Facsimile” of the magazine Denshi Gijutsu, 1988-4, an encoded signal supplied via a system bus is decoded in real time. The decoded image signal is directly outputted to a laser printer without storing it in a page memory.
In the Publication JP-A-62-133865, an image signal of one page can be recorded on two pages and the same partial image can be recorded on both the bottom portion of the first page and the top portion of the second page, by switching between the input image signal and the image signal stored in the image memory.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an image signal processing apparatus and an information transmission and reception apparatus, capable of encoding an image signal into a code signal and decoding a code signal into an image signal to record it, at a high speed.
It is another object of the present invention to provide a high speed image signal processing apparatus and a high speed information transmission and reception apparatus capable of setting the input bit rate of an image signal at least to the coding operation speed while ensuring the reliable transmission and reception of a code signal.
According to one aspect of the present invention, there is provided an image signal processing apparatus comprising: encoding unit having a plurality of line memories for storing an input image signal, the encoding unit encoding the image signal into a code signal while always confirming that the image signal of at least one line is stored in the line memories; and decoding unit having a plurality of line memories for storing the decoded image signal, the decoding unit decoding an input code signal from a page intermediate position as well as one of a page top position.
The decoding unit is connected via an image bus to at least an image memory and a recording unit for recording the image signal, the image memory storing a decoded image signal of a plurality of lines.
The decoding unit includes at least a code analyzer, the plurality of line memories for storing the decoded image signal, a transition point calculator, an image signal recovering unit, a register group, a control sequencer, and a transfer unit, respectively connected to a bus, the code analyzer analyzing the code signal, the transition point calculator calculating a transition point of the code signal related image signal stored in one of the line memory, the image signal recovering unit recovering the image signal from the code signal related image signal at the area from an address one point before the transition point address and to the transition point address, the register groups storing at least the number of lines of the image signal and the transition point address, the control sequencer controlling the sequence of the decoding operation, and the transfer unit transferring the recovered image signal stored in one of the line memories to the image bus via an image bus interface.
The control sequencer includes at least an error detecting unit for detecting an error of the code signal related image signal and informing an error to the transfer unit.
The register group includes a decoded line umber storing register for storing the number of decoded lines of the image signal and a decoded line number managing register for updating the contents of the decoded line number storing register each time one line has been decoded. The decoded line number managing register initializes the contents of the decoded line number register when the decoding operation starts from the page top position, and does not initiate the contents when the decoding operation starts from the page intermediate position.
The register group includes an address register for storing an address of the image signal and a transfer line number register for storing the number of lines of the image signal to be outputted to the recording unit.
The register group includes a first position setting register for storing the position to forcibly change the decoded image into a white pixel signal when the image signal on the line with the error is outputted to the image memory and the recording unit, and a second position setting register for storing the position to forcibly change the decoded image into a black pixel signal when the image signal on the line with the error is outputted to the image memory and the recording unit.
The register group includes a first register for instructing addition of an error mark to the image signal on the line with the error, if the control sequencer instructs the first register to add the error mark, and outputs the image signal with the error mark to the recording unit and the image memory.
The register group includes a register for receiving an instruction to judge whether the decoding operation is continued until an end-of-page signal is received.
The code analyzer includes at least an analyzer sequencer responsive to a decoding instruction from the control sequencer, a code input unit for receiving the code signal in response to a shift instruction from the analyzer sequencer, a final signal detector for decoding a code signal representing an end-of-line, an analyzer table responsive to an operation instruction signal from the analyzer sequencer for receiving the code signal from the code input unit and analyzing the code signal, and an analyzing result latch for temporarily storing the analyzed code supplied from the analyzer table.
The analyzer sequencer includes at least a start instruction setting unit for setting a start of the decoding operation.
The transition point calculator includes at least a transition point address calculator sequencer responsive to an instruction signal from the control sequencer for outputting an operation instruction signal, an analyzed result latch responsive to the operation instruction signal from the calculator sequencer for latching the analyzed result, a decoded line transition point address calculator unit, a reference line access unit responsive to the operation instruction signal from the calculator sequencer for receiving th
Nakamura Kouzou
Yokosuka Yasushi
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Nguyen Madeleine
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