Image sensor with on-chip semi-column-parallel pipeline ADCS

Details Image sensor with on-chip semi-column-parallel pipeline ADCS Image sensor with on-chip semi-column-parallel pipeline ADCS

2004-10-05

2009-08-04

Tran, Nhan T (Department: 2622)

Television

Camera, system and detail

Solid-state image sensor

C348S222100, C341S126000

Reexamination Certificate

active

07570293

ABSTRACT:
An imaging device with a semi-column-parallel pipeline analog-to-digital converter architecture. The semi-column-parallel pipeline architecture allows multiple column output lines to share an analog-to-digital converter. Analog-to-digital conversions are performed in a pipelined manner to reduce the conversion time, which results in shorter row times and increased frames rate and data throughput. The architecture also enhances the pitch of the analog-to-digital converters, which allows high performance, high resolution analog-to-digital converters to be used. As such, semi-column-parallel pipeline architecture overcomes the shortcomings of the typical serial and column-parallel architectures.

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B. Razavi, “Principles of Data Conversion System Design,” IEEE Press, 1995, Chapter 6, pp. 140-143.

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