Image sensor with on-chip semi-column-parallel pipeline ADCs

Details Image sensor with on-chip semi-column-parallel pipeline ADCs Image sensor with on-chip semi-column-parallel pipeline ADCs

2011-04-05

2011-04-05

Ye, Lin (Department: 2622)

Television

Camera, system and detail

Solid-state image sensor

C348S231100, C341S126000

Reexamination Certificate

active

07920196

ABSTRACT:
An imaging device with a semi-column-parallel pipeline analog-to-digital converter architecture. The semi-column-parallel pipeline architecture allows multiple column output lines to share an analog-to-digital converter. Analog-to-digital conversions are performed in a pipelined manner to reduce the conversion time, which results in shorter row times and increased frames rate and data throughput. The architecture also enhances the pitch of the analog-to-digital converters, which allows high performance, high resolution analog-to-digital converters to be used. As such, semi-column-parallel pipeline architecture overcomes the shortcomings of the typical serial and column-parallel architectures.

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