Image analysis – Image sensing
Reexamination Certificate
1999-02-17
2002-10-29
Grant, Jerome (Department: 2624)
Image analysis
Image sensing
C358S482000, C358S483000, C358S474000
Reexamination Certificate
active
06473538
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image sensor having a plurality of photoelectric conversion devices each including a plurality of light-receiving elements and a method of driving the same and, more particularly, to an image sensor having a resolution switching function and a method of driving the same, a photoelectric conversion device used in the image sensor, and an image reading apparatus such as an image scanner, facsimile apparatus, or electronic copying machine for reading a two-dimensional image.
2. Related Background Art
Recently, in the field of data processing systems, one-to-one type image sensors each having a plurality of semiconductor photosensor chips have been extensively developed as one-dimensional image readers in place of reduction-type line sensors each using a conventional optical system.
For example, Japanese Patent Application Laid-Open No. 5-227362 has proposed a contact-type image sensor which has a new resolution control terminal and allows the user to select a desired resolution in accordance with a use condition.
FIG. 1
is a circuit diagram of a contact-type image sensor integrated circuit proposed in Japanese Patent Application Laid-Open No. 5-227362. In this arrangement, a control terminal
125
is formed on an image sensor chip. The user inputs a signal of high or low level to this terminal to select a high or low resolution mode. This will be briefly described with reference to
FIG. 7. A
start pulse SI and a clock pulse CLK are supplied to a shift register group
104
. When a shift register
104
a
is activated in response to the start pulse SI, its output is input to a channel select switch
103
a
via a NOR gate
121
a
and an AND gate
120
a.
The NOR and AND gates
121
a
and
120
a
are turned on to extract a signal from a photocell
101
a
to a signal line
107
a.
The remaining shift registers
104
b
to
104
f
are sequentially activated to output signals from photocells
101
b
to
101
l
to the signal line
107
a
or a signal line
107
b.
When a control signal “H” is input to the control signal input terminal
125
, analog switches
110
a,
110
b,
122
a,
and
122
b
are switched to obtain an image signal at an image output terminal
111
at a read density of 16 dots/mm. When a control signal “L” is input to the control signal input terminal
125
, the analog switch
110
a
is always set in the ON state to obtain an image signal at the image output terminal
111
at a density of 8 dots/mm which is half the density of the photocells
101
a
to
101
l.
That is, although all the photocells
101
a
to
101
l
on the sensor IC are always operating, some outputs are thinned out by the control signal in externally extracting the output image signal. Therefore, the image signal voltage level is always kept constant, and a conventional arrangement can be used for the subsequent image processing circuit.
To meet high-speed operation, for example, Japanese Patent Application Laid-Open No. 2-210950 has proposed an image sensor chip having a means for delaying a start signal, and a contact-type image sensor using this image sensor chip. A constant current circuit is started before a sensor signal is read to achieve a high-speed read. More specifically, there are provided an image sensor chip used in a multichip photoelectric conversion device obtained by arranging a plurality of image sensor chips having light-receiving elements, and a photoelectric conversion device using this image sensor chip, characterized in that a delay means for delaying a start signal for light signal read operation using the light-receiving elements and a constant current circuit having a signal used for the start signal for the image sensor chip and arranged in an amplifier circuit for amplifying the light signal read signal using the light-receiving elements are turned on before the end of the light signal read operation in accordance with a start signal representing the start of delay of the delay means.
Japanese Patent Application Laid-Open No. 2-210949 discloses a one-chip arrangement used in Japanese Patent Application Laid-Open No. 2-210950. More specifically, this reference has proposed an image sensor chip for driving a shift register using an internal clock &PHgr;
1
synchronous with high level of a clock signal and an internal clock &PHgr;
2
synchronous with low level of the clock signal, and a contact-type image sensor using this image sensor chip, thereby realizing a high-speed read at a duty ratio of 100%.
FIG. 2
is an equivalent circuit diagram of an image sensor chip assumed from the contents described in Japanese Patent Application Laid-Open Nos. 2-210949 and 2-210950.
Referring to
FIG. 2
, a plurality of photoelectric conversion devices
1
,
1
′, and
1
″ are mounted on the image sensor chip, and a clock CLK and start pulse SP for driving each photoelectric conversion device are commonly supplied to the photoelectric conversion devices
1
,
1
′, and
1
″. The photoelectric conversion devices
1
,
1
′, and
1
″ respectively comprise N-bit delay means (n-bit preshift registers
2
,
2
′, and
2
″), k-bit shift registers
3
,
3
′, and
3
″, k-bit light-receiving element arrays
4
,
4
′, and
4
″, timing generation circuits
5
,
5
′, and
5
″, and signal output amplifiers
6
,
6
′, and
6
″.
Next-chip start signals
9
,
9
′, and
9
″ output signals N bits ((K-N)th bit) before the end of read by bits of the photoelectric conversion devices as the start signals for the next chips from the bit position N bits before the last register of the shift registers
3
,
3
′, and
3
″.
The timing generation circuits
5
,
5
′, and
5
″ driven by the clock CLK and the start pulse signal SP generate pulses for driving the light-receiving elements
4
,
4
′, and
4
″, and the drive pulses &PHgr;
1
(
7
,
7
′, and
7
″) and &PHgr;
2
(
8
,
8
′, and
8
″) for driving the shift registers
3
,
3
′, and
3
″. The start pulse signal SP is commonly supplied to the respective image sensor chips so as to synchronize the start of operations of the respective image sensor chips.
The signal output amplifiers
6
,
6
′, and
6
″ amplify image signals read from the light-receiving element arrays
4
,
4
′, and
4
″ onto a single signal output line via switches which are turned on/off in accordance with shift signals from the shift registers. The amplified signals are converted into signal outputs Vout in accordance with the control signal from the timing generation circuits
5
,
5
′, and
5
″. Constant current circuits are arranged in the signal output amplifiers
6
,
6
′, and
6
″ and receive the voltage simultaneously with the input of the start signal. The constant current circuits allow the amplifiers to perform steady amplification operations when the clock signals each succeeding N bits from the start signal are input.
FIG. 3
is a timing chart of the drive pulses &PHgr;
1
(
7
,
7
′, and
7
″) and &PHgr;
2
(
8
,
8
′, and
8
″) for the shift register
3
with reference to the clock CLK.
Note that
FIG. 3
shows the timings when the delay means in
FIG. 2
has a 4-bit arrangement. The operation of the first one of the shift register
3
,
3
′, or
3
″ starts with a delay of 4 bits from the start pulse signal SP.
As shown in
FIG. 3
, the drive pulse &PHgr;
1
(
7
,
7
′, and
7
″) is synchronized with high level of the clock CLK, while the drive pulse &PHgr;
2
(
8
,
8
′, and
8
″) is synchronized with low level of the clock CLK. The signal output Vout is extracted in synchronism with the drive pulses &PHgr;
1
, and &PHgr;
2
. When the first bit of the shift register
3
corresponds to the drive pulse &PHgr;
1
, the odd- and even-numbered bits of the signal output are synchronized with the drive pulses &PHgr;
1
and
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Grant Jerome
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