Television – Two-way video and voice communication – Transmission control
Reexamination Certificate
1999-02-08
2003-06-24
Kostak, Victor R. (Department: 2611)
Television
Two-way video and voice communication
Transmission control
C348S207100, C348S014080
Reexamination Certificate
active
06583809
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to an image input apparatus, system, method and storage medium for inputting high-resolution and low-resolution images to a personal computer, for example. The invention further relates to an image sending/receiving system using a low-resolution/high-resolution image input apparatus.
FIG. 13
is an external view of a videoconference system according to the prior art. The system includes a host personal computer
101
having a display
102
, and a video camera unit
103
, which is capable of being controlled by the host personal computer
101
, for inputting moving images to the host personal computer
101
. The video camera unit
103
is mounted on a pan head
110
. An integrated cable
104
connects the host personal computer
101
to the video camera unit
103
. The host personal computer
101
has a keyboard
105
, a mouse (pointing device)
106
, a microphone set
107
and a communications cable
108
.
FIG. 14
is a block diagram showing the flow of various signal in the system of FIG.
13
.
Shown in
FIG. 14
are the video camera unit
103
and pan head
110
. An expansion board
111
for the host personal computer
101
is connected to a PCI bus of the host personal computer
101
.
The video camera unit
103
comprises a lens unit
112
, a lens-unit driver
113
, an image sensing device (e.g., a CCD)
114
, a correlated double sampling circuit
115
, an automatic gain control circuit
116
, an adder
117
, a timing generator
118
, a processing circuit [referred to as a VIDS (Vertical Interval Data Signal)]
119
for sending and receiving data in a video vertical blanking interval, a microprocessor
120
, a microphone
121
and a microphone amplifier
122
.
The expansion board
111
of the host personal computer
101
comprises an A/D converter
123
, a camera process circuit
124
, a video process circuit
125
, a multiplexer/demultiplexer
126
for multiplexing and demultiplexing data, audio and images, a PCI bus controller
127
, a processing circuit (VIDS)
128
for sending and receiving data in a video vertical blanking interval, a synchronizing signal generator (SSG)
129
, a microprocessor
130
, an audio A/D converter
131
, an audio D/A converter
132
, and an audio process circuit
133
.
A CPU
134
constitutes a host computer system including a chip set and a memory, etc., and has a hard disk (HDD)
135
connected thereto via an IDE interface. Applications for image input and videoconferencing have been installed on the hard disk
135
. A communications board
136
is connected to the host computer system.
The general operation of the system constructed as set forth above will now be described.
First, power is introduced to the host personal computer
101
and the videoconferencing application is started up. When the start of videoconferencing is designated by the videoconference application, the CPU (not shown) of the host personal computer
101
sends a prescribed command to the microprocessor
130
of the expansion board
111
so as to turn on the power supply of the video camera unit
103
. In response to an indication from the microprocessor
130
that has received the above-mentioned command in this system, the power supply circuit of the expansion board
111
supplies power to the video camera unit
103
via the integrated cable
104
. (The power supply circuit and power line are not shown.)
The video camera unit
103
thus supplied with power is thenceforth initialized and performs an image sensing operation by processing the command from the microprocessor
130
of the expansion board
111
by the microprocessor
120
of the video camera unit
103
via the VIDS
128
, integrated cable
104
and VIDS
119
. The components of the video camera unit
103
are controlled by commands from the microprocessor
120
. A command in response to various commands from the expansion board
111
is output by the microprocessor
120
, superimposed by the adder
117
upon the vertical blanking interval of a CCD signal adjusted by the correlated double sampling circuit
115
and automatic gain control circuit
116
and sent to the expansion board
111
via the integrated cable
104
. A signal indicating the vertical blanking interval is generated by the SSG
129
on the side of the expansion board and is received by the VIDS
119
on the side of the video camera unit
103
.
The CCD signal resulting from imaging by the video camera unit
103
undergoes correlated double sampling and gain adjustment. The above-mentioned CCD signal is superimposed upon the command by the VIDS
119
in its vertical blanking interval and sent to the expansion board
111
via the integrated cable
104
. The expansion board
111
receives the CCD signal and converts the signal to digital data using the A/D converter
123
.
The image portion of the digital data resulting from the conversion is supplied to the camera process circuit
124
, which serves as signal processing means, and the command portion from the video camera unit
103
is supplied to the microprocessor
130
via the VIDS
128
.
The camera process circuit
124
applies prescribed color processing and white-balance adjustment to the image signal from the video camera unit
103
in digital fashion and outputs Y and U/V signals, which are digital video signals that have been adjusted to a proper level. The camera process circuit
124
extracts a sharpness signal necessary to drive the lens unit
112
and outputs the sharpness signal to the microprocessor
130
. A signal for driving the lens unit
112
is output from the microprocessor
130
to the video camera unit
103
via the VIDS
128
and
119
. The digital Y, U/V signals are supplied to the video process circuit
125
, which serves as image processing means, for being subjected to image-data compression processing and the like for purposes of communication. Here the communication compression scheme used is that for compressing moving images in videoconferencing. The scheme is typified by H261 of ITU-T, by way of example.
Besides being subjected to the above-mentioned compression processing, the digital Y, U/V signals are supplied to the PCI bus controller
127
for transfer to the host computer system
134
.
The input from the microphone
121
of the video camera unit
103
is amplified by the amplifier
122
, after which the amplified signal is input to the adder
137
of the expansion board
111
via the integrated cable
104
. The input from the microphone of the microphone set
107
is amplified by an amplifier
138
of the expansion board
111
and then input to the adder
137
. The adder
137
adds the microphone input from the video camera unit
103
and the microphone input from the microphone set
107
and inputs the sum to the audio A/D converter
131
. The microphone inputs that have been converted to digital data by the audio A/D converter
131
are subjected to prescribed voice-data compression processing by the audio process circuit
133
. Here the voice-data compression scheme used is that for compressing voice in videoconferencing. The scheme is typified by G728 of ITU-T, by way of example.
The above-mentioned compressed voice data and compressed image data are multiplexed together with the control command from the microprocessor
130
by means of the multiplexer/demultiplexer
126
. The multiplexing scheme is that typified by H221 of ITU-T. The multiplexed data is transmitted to the communications board of another party via the communications board
136
and an ISDN line by control executed by the CPU of the host computer system
134
.
The compressed multiplexed data received from the ISDN line is demultiplexed into an image, voice and a control signal by the multiplexer/demultiplexer
126
. The demultiplexed compressed image signal is transmitted to the video process circuit
125
, decompressed and then transmitted from the PCI bus controller
127
to the host computer system
134
via the PCI bus. The demultiplexed compressed voice data is decompressed by the audio process circuit
133
and then t
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Kostak Victor R.
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