Computer graphics processing and selective visual display system – Computer graphics processing – Graphic manipulation
Reexamination Certificate
1998-11-23
2002-01-15
Brier, Jeffery (Department: 2672)
Computer graphics processing and selective visual display system
Computer graphics processing
Graphic manipulation
C348S581000
Reexamination Certificate
active
06339434
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a visual display of digital image data and, more specifically, to methods and circuits for resizing two-dimensional images in either vertical or horizontal or both dimensions, called image scaling, in real time.
2. Description of the Prior Art
Digital image data generally defines one or more frames. A frame is an image displayed for viewing on a display or panel at one time, i.e., a frame of data fits on the display screen or panel. Each frame includes a rectangular array of pixels. Each pixel has one or more values, for example, a gray scale value for a monochrome display or RGB values for a color display. The resolution of the array, i.e., the number of horizontal and vertical pixels, can also be referred to as the image sample rate or resolution. Common display resolutions include those shown in Table 1 indicating the number of pixels in each dimension:
TABLE 1
VGA
640
480
SVGA
800
600
XGA
1024
768
SXGA
1280
1024
UXGA
1600
1200
HDTV
1280
720
Where the resolution or sample rate of the display device matches the resolution of the image data, the data can be displayed directly; if not, it is desirable in many cases that the image be appropriately scaled. Scaling can be done in either vertical or horizontal or both dimensions, and the sample rates can be scaled up or down. Scaling becomes particularly important in connection with pixelated display systems—devices such as liquid crystal display (LCD) projectors, flat panel monitors, PDP, FED, EL, DMD, etc.—that have a fixed pixel structure.
It is generally known that image scaling can be accomplished using sample rate conversion where the sample rate converter scales by a rational number L/M where L and M are positive integers. In this regard, reference is made to U.S. Pat. Nos. 4,020,332, 4,682,301, and 5,355,328. In addition, Schafer and Rabiner, in “A Digital Signal Processing Approach to Interpolation” (Proceedings of the IEEE, Vol. 61, No. 6, pages 692-702, June, 1973), suggest that finite impulse response (FIR) filters with an integer sample rate increase and a integer sample rate decrease can be used to implement a sample rate converter.
U.S. Pat. No. 4,020,332 to Crochiere, et al., describes a means of implementing direct form FIR filters by prearranging the coefficients in a lookup table and sequencing the calculation through these coefficients. The method requires that L and M be integers in order to maintain the fixed coefficient ordering and proper transfer function characteristics. The number of required FIR coefficients is proportionally related to L resulting in a large number of coefficients when fine resampling control is required.
Accordingly, a need remains for improvements in image scaling methods and apparatus. In particular, a need remains for simplifying scaling circuits in order to improve performance and lower cost. A need also remains to provide finer scaling control.
SUMMARY OF THE INVENTION
The present invention includes new methods and apparatus for changing the size of an image represented by a frame of digital data. For example, the dimensions of the frame, typically expressed in pixels, may need to be changed for output to a display device that does not accommodate the dimensions of the original data. With new flat panel display (FPD) technologies emerging as viable alternatives to the cathode ray tube, for example, methods for converting the wide range of image resolutions to match that of a fixed resolution FPD are required. The invention is not merely applicable to individual or still frames. To the contrary, full motion video is a more likely application. While the concepts of resizing graphics data frames are essentially the same for video as for stills, video requires high speed or “real time” operation. To illustrate, a display device might have 1,000 pixels of resolution in both dimensions, for a total of 1 million pixels. To display a video clip of 1 million pixel frames at say, 60 frames per second, requires 60 MHz bandwidth. Accordingly, one object of the present invention is to provide for resizing frames of image data at high speed.
Another aspect of the invention is to improve image resizing by allowing size adjustments by any scaling factor, i.e., by a real number scale factor, as distinguished from prior art solutions that are limited to integer scale factors. The scale factor can be a decimal number of arbitrary precision. Thus, sample rate conversion can be controlled as finely as required. In a presently preferred commercial embodiment of the invention, vertical and horizontal image scaling circuits are independently programmable to provide any scaling factor between {fraction (1/64)}× and 32× although these factors are illustrative rather than critical. Both scaling factors can be changed on a line-by-line or even pixel-by-pixel basis, as further explained below, thereby providing for high-quality image warping.
A further aspect of the invention is to simplify and improve performance of a FIR filter based scaling circuit. Reductions in the required numbers of multipliers and adders contribute to enabling implementation of the new scaling circuits as part of a pixelated display controller ASIC design. Methods and apparatus for implementing these various aspects of the invention are described below after a brief summary of the drawings.
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Greenberg Robert Y.
West Michael G.
Zimmerman Alan L.
Brier Jeffery
Marger Johnson & McCollom PC
Pixelworks
Yang Ryan
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