Image reject circuit using sigma-delta conversion

Details Image reject circuit using sigma-delta conversion Image reject circuit using sigma-delta conversion

2006-12-12

2006-12-12

Burd, Kevin (Department: 2611)

Pulse or digital communications

Receivers

Angle modulation

Reexamination Certificate

active

07149261

ABSTRACT:
In a digital IF downconversion circuit, in-phase and quadrature signal components are processed in the form of a single serial digital bit stream through a set of simple logic in combination with a reconstruction filter. A source digital oscillator supplying digital signal mixers employs an oversampled digital word of four bits in length, all of which are binary weighted, to achieve at least sixteen levels of accuracy for a sine wave mixing signal without significant phase or amplitude error. The mixer mixes the digitized serial bit stream according to the clock with output of a four-bit wide table representing the source oscillator and the in-phase and quadrature signals are recombined digitally, followed by binary weighting using weighted resistors coupled into a filter. Thus, image rejection is a digital function which is unaffected by resistor tolerance.

REFERENCES:
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patent: 5828955 (1998-10-01), Lipowski et al.
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patent: 2002/0105378 (2002-08-01), Tapio
patent: 2004/0223086 (2004-11-01), Jaffe

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