Static information storage and retrieval – Addressing – Sync/clocking
Patent
1994-03-18
1996-01-23
Fears, Terrell W.
Static information storage and retrieval
Addressing
Sync/clocking
365193, G11C 1300
Patent
active
054870518
ABSTRACT:
An electronic data storage memory performs logic operations on the data values existing in its storage cells to eliminate the number of necessary memory accesses during bitblts. The time in which a bitblt can be completed in an image processing system is prolonged because of the number of memory cycles performed during a "raster operation". Thus, to reduce the number of necessary memory cycles, simple logic operations are performed in image processor memory so that a raster operation may take place without having to read, for example, the destination operand from memory. Since a bitblt performs a raster operation on each pixel in the bitblt block, the reduction in memory access time is proportional to the size of the bitblt block.
REFERENCES:
patent: 3737879 (1973-06-01), Greene
patent: 4763251 (1988-08-01), Kauffman, Jr. et al.
patent: 4808986 (1989-02-01), Mansfield et al.
patent: 4816817 (1989-03-01), Herrington
patent: 4823286 (1989-04-01), Lumelsky et al.
patent: 4837563 (1989-06-01), Mansfield et al.
patent: 4845656 (1989-07-01), Nishibe et al.
patent: 4855628 (1989-08-01), Jun
patent: 4860248 (1989-08-01), Lumelsky
patent: 4897636 (1990-01-01), Nishi et al.
patent: 4903217 (1990-02-01), Gupta et al.
Boekelheide Lee
Providenza John R.
Fears Terrell W.
Network Computing Devices, Inc.
LandOfFree
Image processor memory for expediting memory operations does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Image processor memory for expediting memory operations, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Image processor memory for expediting memory operations will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1509863