Television – Image signal processing circuitry specific to television – A/d converters
Reexamination Certificate
1999-01-26
2003-07-08
Miller, John (Department: 2614)
Television
Image signal processing circuitry specific to television
A/d converters
C348S571000, C348S537000, C348S715000
Reexamination Certificate
active
06590616
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image processing apparatus having functions of A-D conversion and D-A conversion, and more specifically pertains to a technique of processing high-frequency image signals.
2. Discussion of the Background
With recent advance in video technology, image signals processed by an image processing apparatus tend to have higher frequency. The higher frequency of image signals requires higher operating frequencies of an analog-to-digital conversion (hereinafter referred to as ‘A-D conversion’) unit and a digital-to-analog conversion (hereinafter referred to as ‘D-A conversion’) unit.
Since there is a limit of enhancing the operating frequencies of the A-D converter and D-A converter, however, it is difficult to carry out A-D conversion and D-A conversion of high-frequency image signals.
The object of the present invention is thus to solve the above problem of the prior art and provide a technique that facilitates A-D conversion and D-A conversion of high-frequency image signals.
SUMMARY OF THE INVENTION
At least part of the above and the other related objects is attained by a first image processing apparatus of the present invention, which includes: a first sampling clock generator that generates Nw first sampling clock signals, which respectively have a first frequency that is synchronous with a first synchronizing signal of a given first analog image signal and phases that are sequentially shifted; and an A-D conversion unit that converts the first analog image signal with respect to Nw pixels into Nw digital image signals, wherein the A-D conversion unit has Nw A-D converters, which commonly receive the first analog image signal and successively carry out A-D conversion of the first analog image signal in response to the Nw first sampling clock signals having the sequentially shifted phases, thereby generating the Nw digital image signals with respect to the Nw pixels, the Nw digital image signals having phases sequentially shifted.
In the above image processing apparatus, since each of the Nw A-D converters carries out A-D conversion at the relatively low first frequency, the input analog image signal having the high frequency can be readily converted to digital image signals.
In accordance with one preferable application of the first image processing apparatus, the first sampling clock generator includes: a first original sampling clock generation circuit that generates a first original sampling clock signal having the first frequency, in response to the first synchronizing signal; and a first sampling clock generation circuit that generates the Nw first sampling clock signals having the sequentially shifted phases, in response to the first original sampling clock signal.
This structure generates the original sampling clock signal, which is synchronous with the synchronizing signal of the analog image signal, in order to facilitate generation of the Nw first sampling clock signals that are synchronous with the synchronizing signal and have the sequentially shifted phases.
In the first image processing apparatus of this structure, it is preferable that the first sampling clock generation circuit initializes the Nw first sampling clock signals having the sequentially shifted phases, in response to a pulse of the first synchronizing signal, so that a fixed phase relationship is attained between the first synchronizing signal and each of the Nw first sampling clock signals having the sequentially shifted phases.
This arrangement enables the Nw first sampling clock signals to respectively hold the fixed phase relations to the synchronizing signal of the analog image signal. Accordingly each of the pixels arranged in time series and included between the pulses of the synchronizing signal of the analog image signal undergoes A-D conversion at a fixed phase.
In the first image processing apparatus discussed above, it is preferable that the first sampling clock generation circuit includes: a first PLL circuit that generates a first dot clock signal having a second frequency suitable for sampling the first analog image signal, in response to the first original sampling clock signal, the second frequency being Nw times the first frequency; and a first sampling clock extraction circuit that extracts the Nw first sampling clock signals, which have the first frequency and the phases sequentially shifted by a period of the first dot clock signal, in response to the first dot clock signal.
The generation of the dot clock signal having the second frequency, which is Nw times the first frequency, facilitates generation of the Nw first sampling clock signals that are suitable for A-D conversion in the Nw A-D converters.
In the first image processing apparatus discussed above, it is also preferable that the first sampling clock generation circuit includes: a first delay clock generation circuit that sequentially delays the first original sampling clock signal to generate the Nw first sampling clock signals having the sequentially shifted phases.
This structure generates the Nw first sampling clock signals without generating the dot clock signal having the relatively high second frequency. The advantage of this structure is that transfer of high-frequency signals is not required through wiring between the respective circuits when the circuits are mounted on a printed board.
In accordance with one preferable application, the first image processing apparatus having any one of the above structures further includes: an image memory that stores digital image signals; and a write control unit that writes the Nw digital image signals output from the A-D conversion unit into continuous storage areas in the image memory.
The write control unit writes the Nw digital image signals with respect to the Nw pixels into the consecutive storage areas of the image memory, so that the digital image signals are stored in the sequence of the original pixel array.
In accordance with another preferable application of the first image processing apparatus having any one of the above structures, the first sampling clock generator includes: a second sampling clock generation circuit that generates Nw second sampling clock signals, which have sequentially shifted phases and maintain fixed phase relations respectively to the Nw first sampling clock signals having the sequentially shifted phases, wherein the A-D conversion unit further includes Nw latch circuits that latch and output the Nw digital image signals, which are output from the Nw A-D converters and have the sequentially shifted phases, in response to the Nw second sampling clock signals having the sequentially shifted phases.
In this structure, the A-D conversion unit outputs the Nw digital image signals, which are output from the Nw A-D converters and have the sequentially shifted phases, in response to the second sampling clock signals that hold the fixed phase relations to the first sampling clock signals.
In the first image processing apparatus of this structure, the write control unit receives the Nw digital image signals supplied from the A-D conversion unit and at least one of the Nw second sampling clock signals, which are supplied from the first sampling clock generator and have the sequentially shifted phases.
This structure enables the write control unit to utilize the signal that is synchronous with the digital image signals output from the A-D converters. This effectively prevents the write control unit from sampling the digital image signals at transitional periods of the data, thereby ensuring sampling of the digital image signals.
In accordance with one preferable application of the first image processing apparatus discussed above, the write control unit includes plural stages of digital image signal phase regulation circuits that cause the Nw digital image signals, which have the sequentially shifted phases and are supplied from the A-D conversion unit, to be output in an identical phase. The plural stages of digital image signal phase regulation circuits have a
Desir Jean W.
Miller John
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
LandOfFree
Image processor and integrated circuit for the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Image processor and integrated circuit for the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Image processor and integrated circuit for the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3014015