Coded data generation or conversion – Digital code to digital code converters – Serial to parallel
Reexamination Certificate
1999-07-26
2001-05-29
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Serial to parallel
C341S155000, C382S304000
Reexamination Certificate
active
06239729
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image processing apparatus having the functions of A-D conversion and D-A conversion as well as to an integrated circuit used therefor. More specifically the present invention pertains to a technique of processing high-frequency image signals.
2. Discussion of the Background
In an image processing apparatus, input analog image signals are converted into digital image signals by an A-D converter. The converted digital image signals undergo a variety of image processing operations and are subsequently returned to analog image signals through D-Aconversion. A resulting image is then displayed on a display device.
The frequency of image signals to be processed by such an image processing apparatus tends to be heightened with the recent advances in video technology. It is accordingly required to enhance the processing speed of the hardware circuit that actualizes the image processing apparatus with an increase in frequency of the image signals. The processing speed of the hardware circuit, however, generally depends upon the performances of the respective devices constituting the hardware circuit, so that it is difficult to process the high-frequency image signals.
SUMMARY OF THE INVENTION
An object of the present invention is thus to provide a technique for readily processing high-frequency image signals.
At least part of the above and the other related objects is attained by a first image processing apparatus, which includes: a first dot clock generation circuit that generates a first dot clock signal, which is synchronous with a first synchronizing signal of a given first analog image signal and has a frequency suitable for sampling the first analog image signal; anA-D converter that quantizes the first analog image signal to convert the first analog image signal into digital image signals, and sequentially outputs the digital image signals for respective pixels sampled in synchronism with the first dot clock signal; a series-to parallel converter having Mw signal hold circuits that respectively and sequentially hold the digital image signals with respect to Mw consecutive pixels, the series-to-parallel converter outputting in parallel the digital image signals with respect to Nw consecutive pixels, where Mw is an integer of not less than 2 and Nw is an integer of not less than 1 but not greater than Mw, Nw representing a number of signal hold circuits that are actually used; a first sampling clock generation circuit that generates a first sampling clock signal, which is synchronous with the first synchronizing signal and has a frequency that is 1/Nw of the frequency of the first dot clock signal; a second sampling clock generation circuit that generates Nw second sampling clock signals where Nw corresponds to the number of the signal hold circuits used, the Nw second sampling clock signals having the frequency of the first sampling clock signal and different phases that are mutually shifted by one period of the first dot clock signal; and a write control signal regulator that regulates the operation of the first sampling clock generation circuit and the second sampling clock generation circuit and supplies the Nw second sampling clock signals to the Nw signal hold circuits, so as to cause the digital image signals with respect to the Nw consecutive pixels to be output from the series-to-parallel converter as one set of digital image signals.
In this image processing apparatus, the Nw signal hold circuits respectively hold the digital image signals with respect to the Nw consecutive pixels, which have been quantized by and output from the A-D converter. The series-to-parallel converter then outputs the digital image signals of the Nw consecutive pixels in parallel as one set of digital image signals. This arrangement enables the digital image signal to be processed at the frequency, which is 1/Nw of the frequency that is the relatively low frequency of the first dot dock signal. The write controller causes the Nw digital image signals thus obtained to be written into consecutive memory areas in the image memory, so that the image signals are stored in the sequence of the original array of pixels in the image memory In this image processing apparatus, the number Nw of the signal hold circuits is regulated according to the frequency of the first analog image signal This enables the digital image signal to be processed at the relatively low frequency of the first sampling clock signal, even when the first dot clock signal has a high frequency This structure ensures processing of the first analog image signal having a wide frequency range from a relatively low frequency to a very high frequency.
In accordance with one preferable application of the present invention, the image processing apparatus further includes a selective control circuit that suspends operation of Mw−Nw) signal hold Sits which are not used, wherein the write control signal regulator controls the selective control circuit according to the number Nw.
This arrangement suspends operation of the (Mw−Nw) signal hold circuits and thus advantageously reduces the power consumption.
In accordance with one preferable application, the image processing apparatus further includes a number determination circuit that determines the number Nw of the signal hold circuits used according to the frequency of the first dot clock signal.
The number determination circuit determines automatically the number Nw of the signal hold circuits according to the frequency of the first dot clock signal or more specifically, for example, based on the relationship between the frequency of the first dot clock signal and signal frequency that enables the digital image signals output from the series-to-parallel converter to be processed in the image processing apparatus. This arrangement ensures automatically processing of the first analog image signal having a wide frequency range from a relatively low frequency to a very high frequency
In the image processing apparatus of the present invention, it is preferable that the Nw second sampling clock signals having the mutually shifted phases are output together with the one set of digital image signals from the image processing apparatus.
This arrangement enables the one set of digital image signals to be securely sampled by utilizing the Nw second sampling clock signals, which have the mutually shifted phases and are used in the Nw signal hold circuits.
In accordance with one preferable application of the image processing apparatus, the second sampling clock generation circuit generates the Nw second sampling clock signals having the mutually shifted phases, in response to the first sampling dock signal and the first dot clock signal.
Alternatively the second sampling clock generation circuit may generate the Nw second sampling dock signals having the mutually shifted phases by successively delaying the first sampling clock signal.
In accordance with another preferable application of the image processing apparatus, the first sampling dock generation circuit further generates a 90-degree phase shift clock signal having a phase difference of 90 degrees from the first sampling dock signal and the second sampling dock generation circuit generates the Nw second sampling dock signals having the mutually shifted phases, in response to the first sampling dock signal and the 90-degree phase shift clock signal.
In any of the above applications, the second sampling clock generation circuit readily generates the Nw second sampling dock signals having the mutually shifted phases. Among the three alternative arrangements of the second sampling clock generation circuit, especially the second and the third arrangements ensure generation of the second sampling dock signals without using the high-frequency first dot clock signal. This advantageously simplifies the structure of the second sampling dock generation circuit.
In accordance with one preferable arrangement of the image processing apparatus, the second sampling
Chang Daniel D.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Seiko Epson Corporation
Tokar Michael
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