Boots – shoes – and leggings
Patent
1994-01-13
1997-02-11
Gordon, Paul P.
Boots, shoes, and leggings
382304, 382307, G05B 1418, H04N 140
Patent
active
056027273
ABSTRACT:
An image processor comprising a plurality of processor elements each having a product sum calculating function. Input switching means are incorporated for selection of image data so that the desired data in an arbitrary processing step of any one processor element can be transferred to an arbitrary processing step of the other processor element. Each processor element includes a data writing line memory, a multiplier for multiplying the output data of the line memory, a register file for storing the multiplied output therein, and an accumulator for calculating the output of the register file. Pipeline processing of the data can be executed in such constitution, and due to the provision of the input switching means in the preceding stage of each processing circuit, the image data can be transferred between the processor elements to consequently realize enhanced general ability for the image processing.
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Proceedings of the IEEE 1989 Custom Integrated Circuits Conference, 15 May 1989, San Diego, CA USA, pp. 24.4.1-24.4.4; Aono K. Et al: "A 30 ns (600 Mops) Image Processor With a Reconfigurable Pipeline Architecture."5
Limbach & Limbach
Shaw, Jr.; Philip M.
Ando Tatsunobu
Kurokawa Noboru
Brown Thomas E.
Gordon Paul P.
Shaw, Jr. Philip M.
Sony Corporation
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