Image analysis – Image transformation or preprocessing – General purpose image processor
Reexamination Certificate
1999-05-07
2003-10-07
Mehta, Bhavesh M. (Department: 2625)
Image analysis
Image transformation or preprocessing
General purpose image processor
C382S320000, C382S315000, C382S206000, C348S294000, C348S249000, C348S236000, C345S177000
Reexamination Certificate
active
06631217
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an image processor for selectively processing for output a two-dimensional image projected onto an image sensor or compressing the two-dimensional image.
BACKGROUND OF THE INVENTION
Description is made hereinafter for an image processor based on the conventional technology. It should be noted that the description of ordinary processing for outputting a two-dimensional image projected onto an image sensor is omitted herein. As literature related to the image processor based on the conventional technology which can output projection data for a two-dimensional image, for example, there is Japanese Patent Laid-Open Publication No. HEI 10-093358.
FIG. 10
shows a configuration of an image processor based on the conventional technology. In
FIG. 10
, designated at the reference numeral
101
is a plurality of unit pixel circuits connected to each other in an array each for outputting a pixel value for one pixel to output lines
103
and
104
, at
102
a vertical scanning circuit for scanning the unit pixel circuits
101
in the vertical direction, at
105
a plurality of offset read circuits provided in each column for inverting either one of the output lines
103
and
104
and connected to the output terminal
106
through a transmission gate, and at
107
a horizontal scanning circuit for scanning the plurality of offset read circuits
105
in the horizontal direction.
FIG. 11
shows a circuit configuration of the unit pixel circuit
101
. In
FIG. 11
, designated at the reference numeral
113
is an optoelectronic transducer for accumulating electric charge of the pixel generated due to the incident light and changing an output potential according to the amount of light, at
112
a MOS transistor for resetting the optoelectronic transducer to a source potential
111
, at
115
and
116
are transistors for negative and positive output respectively for outputting a current flowing through the MOS transistor
114
.
Description is made hereinafter for the operation so as to obtain projection data for a two-dimensional image in the conventional type of image processor configured as described above. At first, each optoelectronic transducer
113
of each of the unit pixel circuits
101
is reset to a source potential
111
(by controlling a signal Vr in the figure). In this state, conductance of the MOS transistor
114
is changed as the electric charge is accumulated in the optoelectronic transducer
113
due to the incident light.
The MOS transistor
114
amplifies output of the optoelectronic transducer
113
, and further a current flowing through the MOS transistor
114
is outputted to an output terminal
117
(corresponding to a signal Vout
1
in the figure) or
118
(corresponding to a signal Vout
2
in the figure) under the control of the transistor
115
for negative output or the transistor
116
for positive output (by controlling a signal Vn or a signal Vp in the figure is controlled) by the vertical scanning circuit
102
.
Then, when each signal Vn or signal Vp in all the rows is scanned by the vertical scanning circuit
102
, each data corresponding to a total sum of currents from all the unit pixel circuits in each column, namely a total sum of pixel values according to the amount of incident light is obtained in each offset read circuit
105
. Then, a one-dimensional projection, namely a projection of a light pattern irradiated onto the two-dimensional unit pixel circuit can be obtained through scanning by the horizontal scanning circuit
107
. As another literature related to the image processor based on the conventional technology which can output projection data for a two-dimensional image, for example, there is Japanese Patent Laid-Open Publication No. HEI 5-111010. It should be noted that the description of ordinary processing for outputting a two-dimensional image projected onto an image sensor is omitted herein.
FIG. 12
shows a configuration of an image processor based on the conventional technology. In
FIG. 12
, each of the reference numerals
120
11
,
120
12
, . . . ,
120
mn
(m and n: arbitrary integers) indicates a structure of a unit pixel referred to as a charge modulation device (CMD), the CMDs are arranged in a matrix, a video voltage VDD is commonly applied to each drain thereof, row lines
122
1
,
122
2
, . . . ,
122
m
, are connected to gates, and column lines
124
1
,
124
2
, . . . ,
124
n
are connected to sources respectively.
The column lines
124
1
,
124
2
, . . . ,
124
n
are connected to a video line (output line for outputting image signal)
130
as well as to a line
132
with a voltage V (≧0) applied thereto through transistors
126
1
,
126
2
, . . . ,
126
n
for column selection (first MOS switches) as well as through transistors
128
1
,
128
2
, . . . ,
128
n
for inverse selection respectively. The video line
130
is grounded through load resistance
134
, and reads a signal through an output terminal
136
. It should be noted that a variable source-voltage pulse train Vs is loaded onto the output terminal
136
by an illustrated external on-chip circuit or some other external circuit.
Further, the row lines
122
1
,
122
2
, . . . ,
122
m
are connected to the vertical scanning circuit
138
, and vertical scan signals &phgr;G
1
, &phgr;G
2
, . . . , &phgr;Gm are applied thereonto respectively, while the gates of the column-selection transistors
126
1
,
126
2
, . . . ,
126
n
as well as of the inverse selection transistors
128
1
,
128
2
, . . . ,
128
n
are connected to the horizontal scanning circuit
140
, and horizontal scan signals &phgr;S
1
, &phgr;S
2
, . . . , &phgr;Sn as well as the inverse signals thereof are applied to the gates respectively. It is assumed that the CMDs are formed on the same substrate and a substrate voltage Vsub (not shown) is applied to the substrate.
In the conventional type of image processor configured as described above, for example, by concurrently setting the signals &phgr;G
1
, &phgr;G
2
, . . . , &phgr;Gm to an ON state with the vertical scanning circuit
138
, all the pixels from the first row to the m-th row each connected to column are selected, and a sum of signal currents is read out. Then, a one-dimensional projection of a light pattern irradiated onto each of the two-dimensional CMDs can be obtained through scanning (by controlling the signals &phgr;S
1
, &phgr;S
2
, . . . , &phgr;Sn) by the horizontal scanning circuit
140
.
As described above, in the conventional type of image processor, the ordinary processing for outputting a two-dimensional image projected onto an image sensor is executable and also the processing for outputting projection data for the two-dimensional image is executable.
However, in the conventional type of image processor, computing is performed by adding (summing) currents of all the pixels constituting each line, and so, the output level when a gradation signal (pixel value) is read out from one pixel is largely different from that when a result of the computing for projection is read out, namely an electric current value for the result of the computing for projection becomes extremely large.
As described above, the fact that an electric current in computing for projection becomes extremely large and so requires a large amount of power.
In addition, in order to suppress the difference between the output level when a gradation signal (pixel value) is read out from a pixel and that when a result of the computing for projection is read out, types of power units (such as a low-potential power unit) are required to be increased.
In addition, output is easily a nonlinear ‘amount of light’בnumber of pixels’ due to saturation of the added currents, there-fore, in order to maintain the linearity, number of pixels capable of being added disadvantageously becomes extremely small.
SUMMARY OF THE INVENTION
It is an object of the present invention to obtain, for the purpose of solving the problems as described above, an image processor in which an output level and a level of power consumption a
Funatsu Eiichi
Kuramochi Souichiro
Kassa Yosef
Leydig , Voit & Mayer, Ltd.
Mehta Bhavesh M.
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
Image processor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Image processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Image processor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3140589