Image processor

Details Image processor Image processor

1998-06-05

2001-02-13

Peng, John K. (Department: 2714)

Television

Basic receiver with additional function

Multimode

C348S571000, C348S714000, C348S500000, C348S014090, C348S014160, C358S404000, C358S405000

Reexamination Certificate

active

06188440

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to an image processor.
Transmissions via communications lines in video conference and in video telephone are slow, and transmission of a tremendous volume of image data requires the process of encoding. ITU-T (International Telecommunication Union—Telecommunication Standardization Sector) Recommendations H.261 and H.263 are known as adoptable encoding methods. These recommendations specify CIF (Common Intermediate Format) and QCIF (Quarter CIF). Whereas a CIF picture is composed of 352×288 pixels, a QCIF picture is composed of 176×144 pixels. The use of BCH (Bose-Chaudhuri-Hocquenghem Code) error correcting codes in sending and receiving encoded data is also specified in these recommendations. In addition, other encoding methods named after the experts groups of ISO (International Organization for Standardization) have been known, and these encoding methods are JPEG (Joint Photographic Coding Experts Group) which is the international standard for color non-moving picture compression and MPEG (Moving Picture Experts Group) which is the international standard for multimedia moving picture compression.
Encoded data, produced by the process of encoding, are converted into analog video signals by the process of decoding. Conventionally, encoders for image encoding have been prepared independently of decoders for image decoding.
Because of such separate preparation, the design cost increases twofold, therefore increasing the cost of image processing systems. Another problem is that it becomes impossible to make an image processor adaptable to a large number of applications.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an image processor capable of performing a plurality of functions with a single piece of hardware.
In order to achieve the object, the present invention provides a novel image processor. More specifically, the flow direction of data is switched while sharing the greatest possible hardware resource between the process of encoding and the process of decoding, in order to make the image processor of the present invention operable as an encoder or decoder.
Additionally, the functions of sending and receiving transmission clock signals are switched such that the image processor of the present invention can operate as a slave device which receives a transmission clock signal from an external device or as a master device which itself transmits a transmission clock signal for synchronous transmission of encoded data.
The present invention can provide (i) a slave encoder's function to transmit encoded data synchronously with a transmission clock signal received from a system controller in charge of controlling the entire image processing system, (ii) a mater encoder's function to transmit to a decoder a transmission clock signal along with encoded data in the absence of a system controller, (iii) a slave decoder's function to receive encoded data sent from an encoder and a transmission clock signal, and (iv) a master decoder's function to transmit a transmission clock signal so that the encoder can output encoded data synchronously therewith. Additionally, switching between the functions of sending and receiving a timing signal indicative of the start or stop of an encoding process can be made.


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