Image processing unit

Television – Camera – system and detail – Solid-state image sensor

Reexamination Certificate

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Details

C348S312000, C348S272000, C348S333010, C382S299000

Reexamination Certificate

active

06867803

ABSTRACT:
In a moving image display mode, CPU commands a selector to input an output signal of a frequency divider to a signal processing part as a synchronous signal. In case of a CCD with G-stripe or Bayer arrangement, the frequency divider divides the frequency of a clock by an odd number (for example, 3 or 5) and the frequency-divided clock is inputted to the signal processing part. This thins out the pixels of image data to {1/(an odd number)} and the image data is inputted to the signal processing part without changing the arrangement of the pixels. The inputted image data is processed at the signal processing part, and then is outputted to the liquid crystal monitor, which displays a moving image.

REFERENCES:
patent: 4907089 (1990-03-01), Yamaguchi et al.
patent: 5206730 (1993-04-01), Sakai
patent: 5909246 (1999-06-01), Terashima
patent: 6130420 (2000-10-01), Tanaka et al.
patent: 6377301 (2002-04-01), Hieda
patent: 6618085 (2003-09-01), Ishimoto
patent: 20010030700 (2001-10-01), Mabuchi et al.
patent: 20020033894 (2002-03-01), Watanabe et al.
patent: 851509 (1996-02-01), None

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