Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-05-11
2004-06-22
Lao, Lun-Yi (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000, C345S092000, C345S204000
Reexamination Certificate
active
06753840
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an image processing circuit and image data processing method suitable for use with an electro-optical device, wherein image signals divided into multiple systems and extending in the time-axial direction and maintaining a constant signal level each unit time are supplied to the data lines at a predetermined timing, and to an electro-optical device using the same, and to an electronic apparatus.
2. Description of Related Art
A conventional electro-optical device, such as an active-matrix liquid crystal display device, is described with reference to FIG.
15
and FIG.
16
. First, as shown in
FIG. 15
, the conventional liquid crystal display device comprises a liquid crystal display panel
100
, a timing circuit
200
, and an image signal processing circuit
300
. Of these, the timing circuit
200
is for outputting timing signals described in greater detail below, to be used at each of the units. Also, a D/A converting circuit
301
within the image signal processing circuit
300
converts image data Da supplied from external equipment from digital signals into analog signals, and thus outputs image signals VID. Further, a phase rendering circuit
302
takes input of single-system image signals VID and can render the signals into N-phase (N=6 in the drawing) image signals, which are then output. The image signals can be rendered into N phases to extend the application time of image signals supplied to thin film transistors (hereafter referred to as “TFT”) in the later-described sampling circuit, thereby sufficiently securing sampling time for data signals in the TFT panel and discharging time thereof.
On the other hand, an amplifying/inverting circuit
303
inverts the polarity of image signals under the following conditions and amplifies the signals as appropriate, and then supplies the signals as phase-rendered image signals VID
1
through VID
6
to the liquid crystal display panel
100
. Polarity inversion refers to a mutual inversion of voltage levels of the image signals, with the center potential of the amplitude thereof as the reference potential. Also, whether or not to perform inversion is determined according to whether the data signal application method is 1) polarity inversion in units of scanning lines, 2) polarity inversion in units of data signal lines, or 3) polarity inversion in units of pixels, and the inversion cycle thereof is set to one parallel scanning period or dot clock cycle.
Referring now to
FIG. 16
, the liquid crystal display panel
100
will be described. This liquid crystal display panel
100
is made up of a device substrate and opposing substrate facing one another across a gap, with liquid crystal filled in this gap. Now, the device substrate and opposing substrate can be formed of quartz substrate, hard glass, or the like.
Of these, regarding the device substrate, multiple scanning lines
112
are arrayed in parallel in the X direction in
FIG. 16
, and orthogonal to this, multiple data lines
114
are arrayed in parallel in the Y direction. Now, the data lines
114
are blocked in units of 6 lines, forming what will be called blocks B
1
through Bm. In the following for the sake of facilitating description, reference to data lines in general will be made with the denoting reference numeral as
114
, but reference numerals
114
a
through
114
f
will be used in the event of indicating specific data lines.
The gate electrode of each TFT
116
, serving as a switching device for example, is connected to each intersection between the scanning lines
112
and data lines
114
, while the source electrodes of the TFTs
116
are connected to the data lines
114
, and the drain electrodes of the TFTs
116
are connected to the pixel electrodes
118
. Each pixel is made up of a pixel electrode
118
, a shared electrode formed on the opposing substrate, and the liquid crystal sandwiched between these electrodes, forming a matrix array at each intersection between the scanning lines
112
and data lines
114
. Also, holding capacity (omitted in drawing) is formed in a state connected to each pixel electrode
118
.
Now, a scanning driving circuit
120
is formed on the device substrate, so as to sequentially output pulse scanning signals to the scanning lines
112
, based on the clock signals CLY from the timing circuit
200
, inverted clock signals thereof CLYinv, transfer starting pulses DY, etc. In more detail, the scanning driving circuit
120
sequentially shifts the transfer starting pulses DY supplied at the start of the vertical scanning period according to the clock signal CLY and the inverted clock signals thereof CLYinv, and outputs these as scanning line signals, whereby the scanning lines
112
are sequentially selected.
On the other hand, the sampling circuit
130
has one sampling switch
131
for each data line
114
at the end of the data lines
114
. The switches
131
are formed of TFTs formed on the same device substrate, and image signals VID
1
through VID
6
are input to the source electrodes of the switches
131
via the image signals supplying lines L
1
through L
6
. The gate electrodes of the six switches
131
connected to the data lines
114
a
through
114
f
of block B
1
are connected to signals lines to which sampling signals S
1
are supplied, the gate electrodes of the six switches
131
connected to the data lines
114
a
through
114
f
of block B
2
are connected to signals lines to which sampling signals S
2
are supplied, and so on up to the gate electrodes of the six switches
131
connected to the data lines
114
a
through
114
f
of block Bm being connected to signals lines to which sampling signals Sm are supplied. Now, the sampling signals S
1
through Sm are each for sampling the image signals VID
1
through VID
6
by block within a horizontal valid display period.
Also, the shift register circuit
140
is formed on the same device substrate, and sequentially outputs the sampling signals S
1
through Sm based on the clock signals CLX, the inverted clock signals thereof CLXinv, and the transfer starting pulses DX and the like from the timing circuit
200
. In more detail, the shift register circuit
140
sequentially shifts the transfer starting pulses DX supplied at the beginning of the horizontal scanning period according to the clock signals CLX and the inverted clock signals thereof CLXinv, and sequentially outputs these as sampling signals S
1
through Sm.
With such a configuration, at the point that the sampling signal S
1
is output, the six data lines
114
a
through
114
f
belonging to the block B
1
have the image signals VID
1
through VID
6
thereof sampled, and the image signals VID
1
through VID
6
are each written to the six pixels of the scanning line currently selected by the corresponding TFTs
116
.
Subsequently, at the point that the sampling signal S
2
is output, the six data lines
114
a
through
114
f
belonging to the block B
2
have the image signals VID
1
through VID
6
thereof sampled, and the image signals VID
1
through VID
6
are each written to the six pixels of the scanning line selected by the corresponding TFTs
116
at that point.
In the same way, at the point that the sampling signals S
3
, S
4
, and so on through Sm are sequentially output, the six data lines
114
a
through
114
f
belonging to the blocks B
3
, B
4
, and so on through Bm have the image signals VID
1
through VID
6
thereof sampled, and the image signals VID
1
through VID
6
are each written to the six pixels of the scanning lines currently selected by the corresponding TFTs
116
. Then, the next scanning line is selected, and the same writing is executed at the blocks B
1
through Bm repeatedly.
With this driving method, the number of tiers of the shift register circuit
140
for performing driving controlling of the switches
131
of the sampling circuit
130
is reduced to ⅙, as compared to the method wherein the data lines are driven according to point sequence. Further, the frequency of the clock s
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