Image analysis – Color image processing – Compression of color images
Reexamination Certificate
1998-10-13
2001-07-31
Tran, Phuoc (Department: 2621)
Image analysis
Color image processing
Compression of color images
Reexamination Certificate
active
06269183
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an image processor, a static image pick-up device and an image processing method whereby output signals of a predetermined number of pixels, outputted with a plurality of color components intermixed, are encoded into compressed forms and then stored in a memory.
BACKGROUND ART
There has heretofore been employed a static image pick-up device. of the type that produces three color image signals by means of red (hereinafter identified simply by R), green (hereinafter identified simply by G) and blue (hereinafter identified simply by B) color filters provided in a single-plate or single-tube image pick-up device. Such a static image pick-up device performs pixel interpolation processing through the use of adjacent pixel signals so as to obtain three color signals for each pixel. In the pixel interpolation processing, data is easier to process as a digital signal, but digitization of image signals as they are will involve an enormous amount of information; hence, it is customary to carry out signal compression through utilization of the redundancy of video signals with a view to saving the storage capacity of a coded image memory for recording image signals and the signal transmission time. Since it is effective in the pixel interpolation to process the three color signals of different characteristics individually according to color, the signal compression is conventionally performed using a coding circuit provided for each color, that is, using coding circuits of three lines.
By the way, such a static image pick-up device involves complex processing for signal compression and has shortcomings of prolonged computing time and increased power consumption accordingly. To solve these problems, a static image pick-up device disclosed in Japanese Pat. Appln. Laid-Open Gazette No. 4-170886 adopts a method which carries out signal compression by a coding circuit of one line after extracting the color image signals for each color.
FIG. 18
is a diagram depicting a color signal extracting method of the static image pick-up device disclosed in the above-mentioned Japanese Pat. Appln. Laid-Open Gazette No. 4-170886. In
FIG. 18
, reference numeral
20
denotes an imaging device covered all over the surface thereof with strip-like color filters of three colors;
21
a
denotes an R component derived from the output signal of the imaging device
20
;
21
b
denotes a G component derived from the output signal of the imaging device
20
; and
21
c
denotes a B component derived from the output signal of the imaging device
20
.
The static image pick-up device disclosed in Japanese Pat. Laid-Open Gazette No. 4-170886 extracts output signals of the respective color components R, G and B individually from the imaging device
20
, then converts them into digital signals, and sequentially compresses the digital signals by a coding circuit of one line, thereafter recording them on a floppy disk, IC card or similar coded image memory for each color.
In the static image pick-up device disclosed in Japanese Pat. Laid-Open Gazette No. 4-170886 with such a construction as described above, it is necessary to read out the image signals directly from the imaging device for each color—this requires the provision of a dedicated imaging device from which image signals can be read out directly for each color and dedicated hardware therefor.
Since only one line of coding circuit suffices for the traditional static image pick-up device, its construction is simplified accordingly; however, the coded image memory needs to store all color signal components of one frame, and hence it is required to have a large storage capacity.
When the static image pick-up device is formed using an image processor, the amount of data that can be stored in the coded image memory is limited, so that large amounts of data cannot be processed in succession—this gives rise to a problem that high-speed continuous shooting is impossible.
Furthermore, when the static image pick-up device is formed using the image processor, no high definition reproduced images can be created because of limitations on the reduction of the area of one pixel of an imaging device using a CCD (Charge Coupled Device) or the like.
Moreover, when the static image pick-up device is formed using the image processor, it necessarily takes a certain amount of time to display reproduced pictures because coding and decoding of image signals consume predetermined amounts of time.
The present invention is intended to solve such problems as mentioned above and to provide a static image pick-up device which enables color image signals to be read out for each color through the use of an ordinary imaging device.
Another object of the present invention is to provide an image processor and an image processing method which can be realized using only one line of coding circuit and a small capacity coded image memory.
Another object of the present invention is to provide a static image pick-up device which permits high-speed continuous shooting.
Another object of the present invention is to provide a static image pick-up device which creates high definition reproduced images.
Still another object of the present invention is to provide a static image pick-up device which produces a high-speed display of reproduced pictures.
BRIEF SUMMARY
The image processor according to the present invention comprises: pixel rearrangement means for rearranging image signals of a predetermined number of pixels composed of a plurality of color components intermixed into a set of unit blocks, each consisting of image signal components of a same color; fixed-length coding means for encoding the image signals rearranged by the pixel rearrangement means into fixed-length codes for each unit block; and a coded image memory for storing the image signals encoded by the fixed-length coding means into fixed-length codes.
With such a construction, image signals of a plurality of intermixed color components in a block can be rearranged by a small capacity line buffer into unit blocks each consisting of the same color components present at adjacent positions, and coding can be achieved using only color image signal data for each color; furthermore, the image processor can be realized using a coding circuit of one line and a small capacity coded image memory. Additionally, a large amount of image data can be stored in the coded image memory without necessitating any particular increase in its capacity, by which high-speed continuous shooting becomes possible.
In the image processor according to the present invention the fixed-length coding means performs fixed-length coding at different compression ratios for each color component.
This ensures efficient coding according to the characteristic of each color component and permits further reduction of the capacity of the coded image memory.
The image processor according to the present invention further comprises a selector provided at a stage preceding the coded image memory, the selector outputting fixed-length coded and non-fixed-length coded image signals selectively.
This makes it possible to change the display system on the display device according as high-speed continuous shooting is performed or not.
In the image processor according to the present invention, the pixel rearrangement means comprises two line buffers, each having 2m lines, when the unit block is formed as a pixel block with m rows and n columns (where m and n are natural numbers).
This permits reduction of the capacity of each line buffer.
In the image processor according to the present invention, the above-mentioned m is 4.
This also permits reduction of the line buffer capacity.
In the image processor according to the present invention, the above-mentioned m is 2a (where a is a natural number) and the pixel arrangement means rearranges the image signals so that the unit block as a rows and 2n columns.
This permits further reduction of the line buffer capacity.
In the image processor according to the present invention, the above-mentioned m is 2a (whe
Matoba Narihiro
Saito Masayuki
Mitsubishi Denki & Kabushiki Kaisha
Tran Phuoc
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