Television – Bandwidth reduction system – Data rate reduction
Reexamination Certificate
1998-06-03
2003-02-25
Rao, Andy (Department: 2713)
Television
Bandwidth reduction system
Data rate reduction
C375S240180, C348S715000, C348S717000
Reexamination Certificate
active
06525773
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image processing device for dividing an image into a plurality of image blocks, encoding the image blocks into image data and decoding the image data back into the image blocks. More particularly, the present invention relates to an image processing device which performs a discrete cosine transform (hereinafter, abbreviated as “DCT”) and an inverse discrete cosine transform (hereinafter, abbreviated as “IDCT”).
2. Description of the Related Art
As a method for compressing and decompressing a moving image, those employing DCT and IDCT have been commonly known. In such a method, a two-dimensional moving image is divided into square-shaped blocks each including N×N pixels (hereinafter, referred to simply as “image blocks”). The image data is compressed or decompressed by performing DCT or IDCT for each block of image data. By decomposing the image data using DCT, low frequency components, essential for reproduction of the image, can be extracted from the image data, since an actual image (or picture) contains only a small amount of high frequency components (e.g., those of the outline of an object). Based on this, image blocks can be compressed into image data.
The DCT and IDCT operations can be represented by the following Expressions (1) and (2), respectively:
F
(
u
,
v
)
=
2
N
∑
x
=
0
N
-
1
∑
y
=
0
N
-
1
C
(
x
)
C
(
y
)
F
(
x
,
y
)
cos
(
2
u
+
1
)
x
π
2
N
cos
(
2
v
+
1
)
y
π
2
N
(
1
)
F
(
x
,
y
)
=
2
N
∑
u
=
0
N
-
1
∑
v
=
0
N
-
1
C
(
u
)
C
(
v
)
F
(
u
,
v
)
cos
(
2
x
+
1
)
u
π
2
N
cos
(
2
y
+
1
)
v
π
2
N
(
2
)
where N denotes the number of pixels in a row or a column in one image block, whereby the total number of pixels in the block is N×N;
F(u,v) denotes image data obtained by DCT, wherein u and v represent a location of the data within the block; and
f(x,y) denotes image data obtained by IDCT, wherein x and y represent a location of the data within the block.
C(k) in Expressions (1) and (2) can be represented by Expression (3) below.
C
(
k
)
=
{
1
2
(
k
=
0
)
1
(
k
=
1
∼
7
)
(
3
)
As is apparent from comparison between Expressions (1) and (2), DCT and IDCT are substantially the same transform operations, and thus can be implemented with the same circuit configuration by changing coefficients. Therefore, while IDCT will be mainly discussed in the following description, such discussion applies also to DCT.
Two-dimensional IDCT, as represented by Expression (2), is typically implemented by twice performing one-dimensional IDCT (as represented by Expression (5) below). Expression (5) is derived from Expression (2) in such a manner, as in the following Expression (4).
f
(
x
,
y
)
=
2
N
∑
v
=
0
N
-
1
C
(
v
)
cos
(
2
y
+
1
)
v
π
2
N
(
2
N
∑
u
=
0
N
-
1
C
(
u
)
F
(
u
,
v
)
cos
(
2
x
+
1
)
u
π
2
N
)
(
4
)
f
(
k
)
=
2
N
∑
n
=
0
N
-
1
C
(
n
)
F
(
n
,
k
)
cos
(
2
k
+
1
)
n
π
2
N
(
5
)
The one-dimensional IDCT of Expression (5) is repeated twice as follows. First, the one-dimensional IDCT is performed along the row (horizontal) direction, and then the one-dimensional IDCT along the column (vertical) direction is performed for the transform results, thereby obtaining a result which is equivalent to what is obtained by a single two-dimensional IDCT operation.
The one-dimensional IDCT, or Expression (5) above, is a simple product sum operation using a cosine function as a coefficient. Therefore, the circuit configuration required for implementing Expression (5) is relatively simple, and two-dimensional IDCT can thus be implemented more easily. Such a technique of repeating a one-dimensional transform twice instead of performing a single two-dimensional transform operation is disclosed in Japanese Laid-open Publication Nos. 7-200539 and 8-44709.
FIG. 19
schematically illustrates an image processing device employing IDCT based on the standard image compression/decompression method, MPEG. The image processing device receives encoded image data by image blocks each including N×N pixels. The image data is further grouped in macroblocks each including up to six data blocks (respectively for luminance data, chromaticity data, and the like). Thus, a macroblock including a plurality of data blocks is input for one image block including N×N pixels. Each data block is passed on from a VLD (Variable Length Decoding) section
101
to an IS (Inverse Scan) section
102
, an IQ (Inverse Quantization) section
103
, an IDCT section
104
and then to an MC (Motion Compensation) section
105
. A certain operation is performed for the transferred data block at each section.
Each of the VLD section
101
, the IS section
102
, the IQ section
103
and the IDCT section
104
processes one data block at a time, and does so only after the preceding section (i.e., a section which processes the block immediately before the subject section) completely processes that particular block. The last section, i.e., the MC section
105
, first receives all data blocks for the macroblock, and then performs an MC operation between the newly-received macroblock of data and the preceding macroblock of data which is input from a memory section
106
, thereby creating and outputting image data corresponding to the image block of N×N pixels.
A control section
107
generally controls the sections
101
to
105
. Since the sections
101
to
104
each require a different amount of time for processing one data block, while the last section, i.e., the MC section
105
, processes data by macroblocks, the control section
107
successively provides respective operation timings for the sections
101
to
105
.
FIG. 20
illustrates a configuration of the IDCT section
104
. The IDCT section
104
includes two one-dimensional IDCT sections
111
and
112
, an inversion memory
113
provided therebetween and a control section
114
.
The IDCT section
104
operates as follows. The one-dimensional IDCT section
111
performs one-dimensional IDCT for a data block. The transform result is temporarily stored in the inversion memory
113
. Then, the one-dimensional IDCT section
112
performs one-dimensional IDCT for the stored transform result, thereby outputting a result which is equivalent to what is obtained by a single two-dimensional IDCT operation. The control section
114
generally controls the sections
111
to
113
.
FIG. 21
is a timing diagram illustrating the operation timings of the respective sections
101
,
103
,
104
and
105
illustrated in FIG.
19
. The IS section
102
is omitted in
FIG. 21
since the operation thereof is negligibly short in time compared to those of the other sections.
As is apparent from this timing diagram, the VLD section
101
first processes a first data block B
1
. After the VLD section
101
completely processes the block B
1
, the IQ section
103
starts to process the block B
1
. Similarly, after the IQ section
103
completely processes the block B
1
, the IDCT section
104
starts to process the block B
1
. Then, after the IDCT section
104
completely processes the block B
1
, the sections
101
to
104
successively process a second data block B
2
, after which the sections
101
to
104
process a third data block B
3
in the same manner. After the first to third data blocks B
1
to B
3
, which correspond to one macroblock in this instance, have all been processed by the respective sections
Kawasaka Yasuki
Yoda Kazuhiko
Birch & Stewart Kolasch & Birch, LLP
Rao Andy
Sharp Kabushiki Kaisha
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