Image processing device and image processing method

Image analysis – Pattern recognition – Feature extraction

Reexamination Certificate

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Reexamination Certificate

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07397951

ABSTRACT:
SRAMs A, B, C, and D having pixel data of each small block of each large block, for example a small block Aijfor the SRAM A, to simultaneously read out a plurality of pixel data in the small block by specifying an address assigned to each small block, and a matrix of coefficient in which a matrix of plural coefficients are arranged are provided. Also provided are a coefficient matrix controller12and an adding section13to multiply the plural coefficients respectively by pixel data corresponding to each thereof and obtain a sum of the multiplied results. Each pixel data of each small block forming one large block, the pixel data being read out from the SRAMs A, B, C, and D, are multiplied by the coefficient matrix rearranged into a predetermined order.

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2003 IEEE International Solid-State Circuits Conference, vol. Forty-Six, ISSN 0193-6530 “Digest of Technical Papers”, Paper 26.7.

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