Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
2001-03-01
2003-10-14
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S660000, C345S694000, C345S690000, C345S699000
Reexamination Certificate
active
06633283
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image processing device and an image processing method, and, in particular, an image processing device and an image processing method of processing images to be displayed on a display device.
Recently, a CRT (Cathode Ray Tube) display device has been widely used as a display device of a host computer such as a personal computer, a work station or the like. However, a flat-panel display devices such as a liquid crystal panel, a plasma display device and so forth have drawn attentions.
A signal provided from a personal computer to a CRT display device or a flat-panel display device is a video signal. The video signal generally includes analog image data, vertical and horizontal synchronization signals (VS, HS signals), or a composite signal which is a combination of these signals.
Such a video signal may have any of different specifications. Sometimes, a personal computer renders a plurality of different resolutions. As these specifications, there are various resolutions such as 320 dots×200 dots, 640×400 dots, 720 dots×400 dots, 640 dots×350 dots, 640 dots×480 dots, 800 dots×600 dots, 1024 dots×768 dots, 1280 dots×1024 dots, and so forth.
A so-called multi-sync CRT display device is used for dealing with these resolutions. The multi-sync CRT display device measures the synchronization signals of the video signal, causes a driving period and a moving width of a scanning line to correspond to the synchronization signals of the video signal, and, thereby, deals with the resolutions. This is possible because the pitch of a shadow mask which determines the minimum display pixel of the CRT display device is smaller than the pixel pitch according to the display resolution of the video signal.
However, with regard to dot-matrix display devices such as a liquid crystal penal, a plasma display device and so forth, because the pixel thereof is larger than that of the shadow mask of the CRT, the processing performed by the multi-sync CRT display device cannot be performed by the dot-matrix display device. Therefore, analog-to-digital conversion is performed on the input analog video signal in synchronization with the resolution (dot clock signal) of the input analog video signal, interpolation is performed so as to generate a signal corresponding to the output resolution of the dot-matrix display device in each of horizontal and vertical directions, and, thereby, display is made by the display device.
2. Description of the Related Art
FIG. 1
is a block diagram showing one example of an image display device in the related art.
In
FIG. 1
, the image display device
20
is a device of driving a dot-matrix display device using an analog image signal, and, performs display based on the image signal from a personal computer
10
. The personal computer
10
includes a VGA (Video Graphics Array) controller
11
built therein. The image signal is provided to the image display device
20
via the VGA controller
11
.
The VGA controller
11
provides RGB (Red, Green, Blue) signals
12
, HS (Horizontal Scan) and VS (Vertical Scan) signals
13
according to the images, to the image display device
20
.
The image display device
20
includes an A-D converter
21
, an image processing part
22
, an LCD panel
23
, PLL (Phase Locked Loop) circuits
24
,
26
, and a system control part
25
.
The analog video signals (RGB signals
12
and HS and VS signals
13
) are provided to the A-D converter
21
, and the HS and VS signals
13
are also provided to the system control part
25
.
The A-D converter
21
converts the analog video signals from the VGA controller
11
into digital signals in synchronization with a clock signal from the PLL circuit
24
.
The system control part
25
controls the PLL circuits
24
,
26
, A-D converter
21
and image processing part
22
in synchronization with the HS and VS signals
13
.
The PLL circuit
24
provides a clock signal in phase with the HS and VS signals from the system control part
25
, to the A-D converter
21
, and controls the conversion timing of the A-D converter
21
.
The PLL circuit
26
provides the clock signal in phase with the HS and VS signals from the system control part
25
, to the image processing part
22
and LCD panel
23
, and controls the driving timing of the image processing part
22
and LCD panel
23
.
The image processing part
22
converts the digital signals given from the A-D converter
21
into signals of resolution corresponding to the LCD panel
23
using a control signal from the system control part
25
and the clock signal from the PLL circuit
26
. The image processing part
22
includes a FIFO (First-In-First-Out) built therein, and stores the thus-converted signals into the FIFO. These image signals are provided to the LCD panel
23
.
The LCD panel
23
holds data of the image signals given by the image processing part
22
in response to the clock signal given by the PLL circuit
26
, and performs display based on the held data.
FIG. 2
is a block diagram showing another example of an image display device in the related art.
In
FIG. 2
, the image display device
30
is a device of driving a dot-matrix display device using digital image signals, and, performs display based on the image signals from a personal computer
15
. The personal computer
15
includes a VGA (Video Graphics Array) controller
16
built therein. The image signals are provided to the image display device
30
via the VGA controller
16
. The VGA controller
16
provides the RGB (Red, Green, Blue) signal
17
, DE (Data Enable), CLK, HS and VS signals
18
according to the images, to the image display device
30
.
The image display device
30
includes an image processing part
31
, an LCD panel
32
, a PLL (Phase Locked Loop) circuit
34
and a system control part
33
.
The video signals (RGB signal
17
and DE, CLK, HS and VS signals
18
) are provided to the image processing part
31
, and DE, CLK, HS and VS signals
18
are also provided to the system control part
33
.
The system control part
33
controls the PLL circuit
34
and image processing part
31
in synchronization with the DE, CLK, HS and VS signals
18
.
The PLL circuit
34
provides a clock signal in phase with the DE, CLK, HS and VS signals from the system control part
33
, to the image processing part
31
and LCD panel
32
, and controls the driving timing of the image processing part
31
and LCD panel
32
.
The image processing part
31
converts the digital signals given from the VGA controller
16
into signals of resolution corresponding to the LCD panel
32
using a control signal from the system control part
33
and the clock signal from the PLL circuit
34
. The image processing part
31
includes a FIFO (First-In-First-Out) built therein, and stores the thus-converted signals into the FIFO. These image signals are provided to the LCD panel
32
.
The LCD panel
32
holds data of the image signals given by the image processing part
31
in response to the clock signal given by the PLL circuit
32
, and performs display based on the held data.
FIGS. 3A through 3F
show waveforms of the digital signals in the related art.
FIG. 3A
shows the VS signal input to the image processing part
31
shown in
FIG. 2
;
FIG. 3B
shows the DE signal;
FIGS. 3C and 3D
show the HS signal,
FIG. 3E
shows the video (RGB) signal and
FIG. 3F
shows the DE signal. In this example, it is assumed that the input video signal is of VGA mode (640×480 dots, 75 Hz), for example.
The VS signal shown in
FIG. 3A
has a pulse wave having a period of 13.3 ms. When the VS signal has the high level, a vertical scanning signal updating an image is input.
The DE signal shown in
FIG. 3B
has a synchronization interval when the VS signal has the low level, and has a vertical back-porch interval immediately after the VS signal rises up from the low level to the high level. The DE signal has a vertical effective image interval after the vertical back-porch interval
Fukuda Takatoshi
Hagiwara Kunihiko
Hibi Michio
Suzuki Manabu
Toda Seiji
Fujitsu Limited
Staas & Halsey , LLP
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