Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
2000-01-28
2004-12-14
Wu, Xiao (Department: 2674)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S042000, C345S211000, C345S214000, C345S519000, C345S698000, C348S536000, C348S540000, C348S547000, C713S400000, C713S500000, C713S501000, C386S349000, C711S167000, C711S170000
Reexamination Certificate
active
06831634
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image processing device for converting image signals having various formats to image signals in a desired format or for synthesizing the image signals.
2. Related Background Art
The development of multimedia in recent years provides occasions in which images in various image signal formats are displayed on a display screen. Particularly, while a display of a TV set had once been quite different from that of a personal computer (PC), a TV capable of displaying PC images and a PC display to which TV signals can be entered have appeared due to an advancement of their unification. In addition, due to an appearance of video sources in new digital formats such as a digital television or MPEG or due to an advancement of three-dimensional graphics, motion picture is more frequently displayed also on PC displays.
FIG. 6
shows a block diagram of the conventional display. In this drawing, there are shown an analog image signal input terminal
1
-
1
, a horizontal synchronizing signal (IHD) input terminal for input signals
1
-
2
, a vertical synchronizing signal (IVD) input terminal for input signals
1
-
3
, an AD converter
2
for converting analog image signals inputted to the input terminal
1
-
1
to n-bit digital signals, an input system image processing unit
3
, a memory control unit
4
, a memory unit for storing image data
5
, an output system image processing unit
6
, an image display unit
7
, data buses
20
-
1
,
20
-
2
,
20
-
3
, and
20
-
4
for transmitting n-bit digital signals to respective units, a control bus
21
comprising memory control lines and address lines, and a memory data bus
22
.
Reference numeral
8
designates a phase locked loop (PLL) circuit and reference character ICK designates an input system clock synchronized with an input IHD. Further, there are shown an oscillator circuit
12
which generates output system clocks OCK, an H-counter and V-counter circuit
11
which generates output system horizontal synchronizing signals OHD and vertical synchronizing signals OVD based on the output system clock OCK, a microcomputer (&mgr;COM) unit
9
, and m control buses for controlling respective units
19
.
Digital image signals are subjected to image quality adjustment, image reducing conversion, or other processing in the input system image processing unit
3
before being stored in the memory unit
5
and then transferred to the memory control unit
4
. The memory control unit
4
stores image data into the memory unit
5
at a timing corresponding to an input synchronizing signal (IHD, IVD) and an input system clock ICK and transfers the image data from the memory unit
5
to the readout output system image processing unit
6
at a timing corresponding to a horizontal synchronizing signal OHD and a vertical synchronizing signal OVD. The image processing unit
6
adjusts image qualities and converts images with enlargement. Accordingly, input images having various input system formats are converted to image signals having a format appropriate for the image display unit
7
via the memory.
Furthermore recently in a wide-screen display device such as a wide-screen television, a plasma display, a rear projection-type TV, or a front projection-type projector, there has been an increase of situations in which various video sources such as films, televisions, home videos, presentations, TV conferences, and displays of various materials are used in offices or houses. In addition among these types of displays, there is a display having a multi-screen display function of displaying a plurality of images from different input sources on a single screen with the screen divided.
FIG. 13
shows as an example of a display conventionally used in this situation a block diagram of an image processing unit of an image display device having one system for an input of digital computer image signals and the other system for two-system PC inputs which are analog computer image signal inputs, in which outputs of a frame memory are controlled for synchronization so as to perform a multi-screen display having two screens in a single-system image display unit.
In
FIG. 13
, there is shown an input terminal
1
-
1
a
for q-bit digital computer image signals (IDATA
1
) of a first system (PC
1
). While intrinsically a description should be made for three systems of red, blue, and green (RGB), only one system is used here for a simple description of a configuration (the same shall apply hereinafter). There are also shown an input horizontal synchronizing signal (IHD
1
) input terminal
1
-
1
b
, an input vertical synchronizing signal (IVD
1
) input terminal
1
-
1
c
, an image signal clock (ICK
1
) input terminal
1
-
1
d
, and a DDC (DDC
1
) input-output terminal
1
-
1
e
, data buses
20
-
1
a
-
1
and
20
-
1
a
-
2
for transmitting q-bit digital image signals to respective units. In addition, there are shown IHD
1
, IVD
1
, ICK
1
, and DDC
1
signal lines
20
-
1
b
,
20
-
1
c
,
20
-
1
d
, and
20
-
1
e
, respectively.
DDC is a standard for communication means for computers to recognize or control displays recommended by a standardizing organization, a Video Electronic Standard Association (VESA).
There are also shown an input terminal
1
-
2
a
for analog computer image signals (IDATA
2
) of a second system (PC
2
), an input horizontal synchronizing signal (IHD
2
) input terminal
1
-
2
b
, an input vertical synchronizing signal (IVD
2
) input terminal
1
-
2
c
, and a DDC (DDC
2
) input-output terminal
1
-
2
e.
An AD converter
2
converts an analog image signal (IDATA
2
) to an n-bit digital signal. A PLL circuit
8
generates input system clocks (ICK
2
) in a PC
2
side synchronized with horizontal synchronizing signals (IHD
2
) inputted from the terminal
1
-
2
b.
Reference numeral
20
-
2
a
-
0
designates an analog signal line and reference numerals
20
-
2
a
-
1
and
20
-
2
a
-
2
designate n-bit digital signal lines. Reference numerals
20
-
2
b
,
20
-
2
c
,
20
-
2
d
, and
20
-
2
e
designate signal lines for IHD
2
, IVD
2
, ICK
2
, and DDC
2
, respectively.
There are also shown a PC
1
input system image processing unit
3
-
1
, a memory control unit
4
for a control of storing image signals inputted from the two-system input image processing units in a memory once and synthesizing images and outputting them to an output system image processing unit so as to output them on a multi-screen, frame memories (memory A, memory B)
5
-
1
and
5
-
2
corresponding to input systems PC
1
and PC
2
, respectively, control buses
21
-
1
and
21
-
2
for the memory A and the memory B, respectively, and data buses
22
-
1
and
22
-
2
for the memory A and memory B, respectively.
A microcomputer unit
9
controls a system and microcomputer buses (MB)
19
-
1
and
19
-
2
comprise control lines from a microcomputer to respective units and data lines.
An oscillator circuit
12
generates output system clocks (OCK).
A H-counter and V-counter unit
11
counts output system clocks (OCK) and generates horizontal synchronizing signals (OHD) and vertical synchronizing signals (OVD) of the output system.
Additionally there are shown an output system image processing unit
6
and an image display unit
7
such as a plasma display and a CRT.
Reference characters
1
-
f
,
1
-
g
,
1
-
h
,
1
-
i
, and
1
-
j
designate an input terminal of an image display unit for image display digital data (ODATA), an input terminal of an image display unit for output horizontal synchronizing signals (OHD), an input terminal of an image display unit for output vertical synchronizing signals (OVD), an input terminal of an image display unit for output image signal clock (OCK), and an input terminal of an image display unit for microcomputer buses (MB), respectively.
Furthermore,
20
-
f
-
1
,
20
-
f
-
2
, and
20
-
f
3
are signal lines for k-bit ODATA and
20
-
g
-
1
and
20
-
g
-
2
are signal lines for OHD.
20
-
h
-
1
and
20
-
h
-
2
are signals lines of OVD and
20
-
i
-
1
and
20
-
i
-
2
are sign
Abdulselam Abbas
Wu Xiao
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