Image processing device

Computer graphics processing and selective visual display system – Computer graphic processing system – Interface

Patent

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Details

345509, 345515, 345517, 345422, G06F 1316

Patent

active

059823984

ABSTRACT:
An image processing apparatus performs one of reading and writing of pixel data for a predetermined number of pixels at one access to a frame buffer which stores the pixel data, the frame buffer comprising a memory to which access in a page mode can be performed. A pixel buffer portion comprises a plurality of stages of pixel buffers, each thereof storing the pixel data for the predetermined number of pixels. A memory interface determines the number of pixel data which is processed successively, based on the pixel data stored in each stage of the pixel buffer, and, in accordance with the determined number of pixel data, determines the number of times of CAS, which is the number of accesses which are performed successively for the same row address in one page mode operation when data is written in the frame buffer.

REFERENCES:
patent: 5036475 (1991-07-01), Ueda
patent: 5459834 (1995-10-01), Katayama
patent: 5459842 (1995-10-01), Begun et al.
patent: 5585863 (1996-12-01), Hackett et al.
patent: 5828378 (1998-10-01), Shiraishi

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