Image processing circuit, imaging circuit, and electronic...

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

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Details

C341S164000, C341S169000, C348S222100, C348S241000, C348S308000

Reexamination Certificate

active

07345613

ABSTRACT:
An image processing circuit for reducing noise. The image processing circuit includes a CDS circuit for taking a potential difference between a pixel signal at a reset of an image pickup device and a pixel signal after exposure, and an AD conversion circuit. The AD conversion circuit includes an increment counter and AD conversion clock provided for the AD conversion of the potential difference of the image pickup device between at a reset and after exposure, and an averaging ADC control circuit for averaging a plurality of digital code values obtained through the AD conversion repeated a plurality of times.

REFERENCES:
patent: 5946033 (1999-08-01), Mooney et al.
patent: 6774941 (2004-08-01), Boisvert et al.
patent: 7075474 (2006-07-01), Yamagata et al.
patent: 2006/0114342 (2006-06-01), Egawa
patent: 2006/0170795 (2006-08-01), Higuchi et al.
patent: 2007/0080842 (2007-04-01), Kawahito
patent: 2001-203936 (2001-07-01), None
patent: 2005-136540 (2005-05-01), None

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