Television – Camera – system and detail – Combined image signal generator and general image signal...
Reexamination Certificate
1999-11-23
2004-01-06
Garber, Wendy R. (Department: 2612)
Television
Camera, system and detail
Combined image signal generator and general image signal...
C348S223100, C348S655000, C348S659000, C348S661000, C348S029000
Reexamination Certificate
active
06674465
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method and an apparatus for processing image data, and, more particularly, to an image data processing method which generates primary color data representing primary color components from complementary color data representing complementary color components.
FIG. 1
is a block diagram showing the configuration of a prior art image sensing device
100
which uses a CCD image sensor
1
, and
FIG. 2
is a plane view showing an example of a mosaic color filter attached to the CCD image sensor
1
.
The CCD image sensor
1
has a plurality of light-receiving pixels, a plurality of vertical shift registers and usually a horizontal shift register. The light-receiving pixels are arranged in a matrix form on the light-receiving surface at regular intervals and produce and store information charges corresponding to the image of each sensed object. The vertical shift registers are arranged to correspond to the columns of the light-receiving pixels and sequentially shift the information charges stored in the light-receiving pixels, in the vertical direction. The horizontal shift register is arranged on the output side of the vertical shift registers and receives the information charges output from the vertical shift registers, and then transfers the information charges row by row. This allows the horizontal shift register to output an image signal I
0
which changes a voltage value in accordance with the information charges stored in the light-receiving pixels.
An analog processing circuit
2
performs a process, such as sampling and holding or level clamping, on the image signal I
0
input from the CCD image sensor
1
to produce an image signal I
1
which conforms to a predetermined format. For example, in the sample and hold process, only an image signal having a certain signal level is extracted from the image signal I
0
having reset levels and signal levels which are alternately repeated in synchronism with the output operation of the CCD image sensor
1
. In the level clamping process, the black reference level set at the end of the horizontal scanning period of the image signal I
0
is clamped to a predetermined level every horizontal scanning period. An A/D conversion circuit
3
quantizes the image signal I
1
received from the analog processing circuit
2
in synchronism with the operation of the analog processing circuit
2
, i.e., the output operation of the CCD image sensor
1
, to generate image data D which represents the information with a digital value corresponding to each light-receiving pixel of the CCD image sensor
1
.
A digital processing circuit
4
performs a process, such as color distribution or a matrix operation, on the image data D received from the A/D conversion circuit
3
and generates luminance data Y and color difference data U and V. For example, in the color distribution process, the image data D is separated in accordance with the color arrangement of a color filter attached to each light-receiving surface of the CCD image sensor
1
, generating a plurality of color component data. Further, in the matrix operation process, primary color data corresponding to the three primary colors of light are generated from the individually separated color component data, and are then combined at a predetermined ratio, thereby generating the color difference data.
A driver
5
responds to various timing signals from a timing control circuit
6
and supplies a multi-phase drive clock to each shift register of the CCD image sensor
1
. For example, a 4-phase vertical transfer clock &phgr;v is supplied to the vertical shift registers, and a 2-phase horizontal transfer clock &phgr;h is supplied to the horizontal shift register. In accordance with a reference clock having a given period, the timing control circuit
6
produces a vertical timing signal, which determines the vertical scan timing of the CCD image sensor
1
, and a horizontal timing signal, which determines the horizontal scan timing, and supplies the timing signals to the driver
5
. At the same time, the timing control circuit
6
supplies a timing clock CT for synchronizing the operation of each circuit
2
,
3
,
4
with the output operation to the analog processing circuit
2
, the A/D conversion circuit
3
and the digital processing circuit
4
.
In performing color image sensing, attaching a color filter for color distribution to the light-receiving surface allows the individual light-receiving pixels of the CCD
1
to be associated with predetermined color components. A stripe type color filter has a plurality of segments each of which is connected in the vertical direction and a mosaic type color filter which has a plurality of segments associated with every light-receiving pixel. For example, the mosaic type color filter, as shown in
FIG. 2
, is split into a plurality of segments corresponding to each pixel of the light-receiving section of the CCD image sensor
1
and color components of Ye (yellow), Cy (cyan), W (white) and G (green) are cyclically assigned to each segment. In the example of
FIG. 2
, the W and G components are alternately arranged in odd rows and the Ye and Cy components are alternately arranged in even rows. For an image signal obtained from the CCD image sensor
1
to which such color filter is attached, the W and G components are repeated when reading even rows and the Ye and Cy components are repeated when reading odd rows.
FIG. 3
is a block diagram showing the configuration of the digital signal processing section
4
, and
FIG. 4
is a timing diagram for describing the operation of the processing section
4
.
FIG. 4
corresponds to the case where the mosaic type color filter shown in
FIG. 2
is attached to the CCD
1
.
A color distribution circuit
11
separates the image data D in which each color component continues in the arrangement order of each segment of the color filter. The distribution circuit
11
then generates color component data C[Ye], C[Cy], C[G] and C[W]. For the image data D input from the A/D conversion circuit
3
, as shown in
FIG. 4
, the G and W components continue alternately in an operation of reading odd rows (ODD) and the Ye and Cy components continue alternately in an operation of reading even rows (EVEN). Accordingly, the color distribution circuit
11
retains at least one row of the image data D to allow the output of all the color component data C[Ye], C[Cy], C[G] and C[W] at the time of reading each row. Specifically, during reading of an odd row, the color distribution circuit
11
separates the image data D for the odd row and outputs the color component data C[G] and C[W]. At the same time, the color distribution circuit
11
separates the image data D for the previously read even row and outputs the color component data C[Ye] and C[Cy]. Further, this scheme causes the color component data C[Ye], C[Cy], C[G] and C[W] to be output intermittently at the time of outputting the image data D serially. The intermittent portions of the color component data are however interpolated by outputting the same color component data twice in succession.
A color calculation circuit
12
performs a color computation process according to, for example, the following equations on the color component data C[Ye], C[Cy], C[G] and C[W] input from the color distribution circuit
11
, to generate primary color data P[R], P[G] and P[B] corresponding to the three primary colors (R: red, G: green and B: blue) of light.
Ye−G=R
Cy−G=B
G=G
A white balance control circuit
13
assigns specific gains set to each of the primary color data P[R], P[G] and P[B] input from the color calculation circuit
12
to adjust the balance of each color. In other words, in the white balance control circuit
13
, because this adjust
Garber Wendy R.
Hannett James
Sanyo Electric Co,. Ltd.
Sheridan Ross PC
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