Image analysis – Image transformation or preprocessing – Changing the image coordinates
Reexamination Certificate
1998-05-04
2001-01-30
Mehta, Bhavesh (Department: 2721)
Image analysis
Image transformation or preprocessing
Changing the image coordinates
C358S451000
Reexamination Certificate
active
06181833
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image processing apparatus which may be advantageously incorporated in a facsimile machine or any other machine which requires an image reducing and enlarging function.
2. Description of the Related Art
An image processing apparatus is used for various purposes. For example, it may be used for reducing and/or enlarging the images obtained by an image sensor. It may be also used for performing &ggr;-control, color control, image sharpening and etc.
In a prior art image processing apparatus, image reduction and/or enlargement in the primary and secondary scanning directions is performed together at the time of storing the image data in a buffer memory or reading out the image data from the memory. Thus, the image processing apparatus requires a high-speed CPU for software processing or a large scale circuit for hardware processing, which results in a cost increase. This is particularly critical in the case of processing color images because different color sets of digitized image data (namely, a large amount of digitized image data) need to be processed.
Further, in the case of enlarging color images in both scanning direction at the time of writing the image data in the buffer memory, the capacity of the buffer memory must be large enough for storing a large amount of image data with a high efficiency and a high processing speed. The use of such a buffer memory will also lead to a cost increase.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention is to provide an image processing apparatus which is capable of reducing and enlarging the image without entailing a cost increase problem.
Another object of the present invention is to provide an image processing apparatus which is capable of extracting the image data at high speed in sequence suitable for additional image processing.
According to a first aspect of the present invention, there is provided an apparatus for processing an image comprising: a memory for storing a set of image data which includes plural groups of image data, each group of image data corresponding to a line of pixels arranged in one scanning direction which is perpendicular to another scanning direction; a writing reducer for reducing the image in said another scanning direction by deleting selected groups of image data before storing the set of image data in the memory; and a reading reducer-enlarger for enlarging the image in said another scanning direction and for reducing or enlarging the image in said one scanning direction at the time of reading out the stored set of image data from the memory.
With the image processing apparatus described above, the writing reducer provides image reduction in said one scanning direction before data storage in the memory, whereas the reading reducer-enlarger provides image enlargement in said one scanning direction and image reduction or enlargement in said another direction at the time of reading out the stored set of image data from the memory. Thus, compared with the prior art wherein image reduction and/or enlargement in both scanning directions is performed together at the time of storing the image data in the memory or reading out the image data from the memory, the image processing apparatus does not require a high-speed CPU or a large scale circuit, thereby realizing a cost reduction. Further, the memory does not need to have a large capacity even when the image is enlarged in both scanning directions, because such image enlargement is performed only at the time of reading out the set of image data from the memory.
Typically, said one scanning direction may be a primary scanning direction in which the image pickup elements of an image sensor are arranged, whereas said another scanning direction may be a secondary scanning direction in which a document paper is moved relative to the image sensor. Further, the writing reducer may be provided by a writing reduction circuit, whereas the reading reducer-enlarger may be provided by a reading reduction-enlargement circuit.
Preferably, the writing reduction circuit may be supplied with line-start signals and clock signals of a predetermined frequency. Further, the writing reduction circuit may comprise a setting register for presetting a reduction ratio, a secondary scanning address generating circuit for generating a secondary scanning address which increases by a predetermined amount in synchronism with the clock signals upon input of a number of line-start signals determined according to the preset reduction ratio, and a primary scanning address generating circuit for generating a primary scanning address which increases one by one in synchronism with the clock signals.
Preferably, the secondary scanning address generated by the secondary scanning address generating circuit may start increasing from a first initial value and returns to the first initial value when a predetermined number of groups of image data are processed, whereas the primary scanning address generated by the primary scanning address generating circuit may start increasing from a second initial value and return to the second initial value when all image data in each group of image data are processed.
Preferably, the reading reduction-enlargement circuit may comprise a secondary direction enlargement circuit portion for enlarging the image in the secondary scanning direction by repetitively reading out each group of image data from the memory. For this purpose, the secondary direction enlargement circuit portion of the reading reduction-enlargement circuit may be supplied with line-start signals and clock signals of a predetermined frequency. Further, the secondary direction enlargement circuit portion may comprise a setting register for presetting an enlargement ratio, and a secondary scanning address generating circuit for generating a secondary scanning address which increases by a predetermined amount in synchronism with the clock signals upon input of a number of line-start signals determined according to the preset enlargement ratio.
On the other hand, the reading reduction-enlargement circuit may also comprise a primary direction reduction-enlargement circuit portion for reducing the image in the primary scanning direction by skipping selected pixel image data in each group of image data at the time of reading out the stored set of image data from the memory and for enlarging the image by repetitively reading out each pixel image data in each group of image data from the memory. More specifically, the primary direction reduction-enlargement circuit portion may comprise a setting register for presetting a reduction or enlargement ratio, and a primary scanning address generating circuit for generating a primary scanning address used for reading out the stored set of image data from the memory.
In operation, the primary scanning address generating circuit may be supplied with a flag. When the flag is in a first state (e.g., high level), the primary scanning address generating circuit enlarges the image in the primary scanning direction by repetitively reading out each pixel image data in each group of image data from the memory in accordance with the preset enlargement ratio. When the flag is a second state (e.g., low level), the primary scanning address generating circuit reduces the image in the primary scanning direction by skipping selected pixel image data in each group of image data in accordance with the preset reduction ratio at the time of reading out the stored set of image data from the memory.
In a preferred embodiment, the primary direction reduction-enlargement circuit portion of the reading reduction-enlargement circuit is supplied with clock signals of a predetermined frequency, and the primary direction reduction-enlargement circuit portion further comprises a frequency divider for dividing the frequency of the clock signals, whereby the primary scanning address generating circuit reads out the stored set of image data from the memory in synchronism with the div
Brother Kogyo Kabushiki Kaisha
Mehta Bhavesh
Oliff & Berridg,e PLC
Patel Kanji
LandOfFree
Image processing apparatus wherein the image data is reduced... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Image processing apparatus wherein the image data is reduced..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Image processing apparatus wherein the image data is reduced... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2477402