Boots – shoes – and leggings
Patent
1990-02-12
1993-08-17
Clark, David L.
Boots, shoes, and leggings
364769, 340750, G06F 1566
Patent
active
052376567
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
This invention relates to an image processing apparatus and, more particularly, to an image processing apparatus capable of executing operations between images at high speed.
BACKGROUND OF THE INVENTION
In various types of image processing for varying picture contrast or extracting the characteristics of an image, a look-up table (LUT) capable of executing image processing simply and at high speed is conventionally used.
The look-up table consists primarily of a RAM, in which the image data of each pixel is inputted as an address. The result of an operation in accordance with a prescribed function in which the address value serves as a variable is stored in each storage area in advance, with the results of the operation being output as data.
When an operation is performed between two images, a dyadic look-up table (D-LUT) is used. The input side of this look-up table is divided into an upper order address input and a lower order address input, and the image data of each pixel of the two images are applied to respective ones of the inputs. The result of an operation in accordance with a prescribed function for the two inputs is stored at an address in which the higher order and lower order addresses are serially connected. For example, if the upper order address is A.sub.U, the lower order address is A.sub.L and the function is f(x,y), then an operational result f(A.sub.U,A.sub.L), which is obtained when x=A.sub.U, y=A.sub.L hold, is stored at an address [A.sub.U A.sub.L ].
For a simple computation such as an arithmetic operation, the operation can be completed in a single cycle by using a look-up table (LUT) or dyadic look-up table (D-LUT). However, when an item of image data of one image is a variable I1 and an item of image data of the other image is a variable I2, an operation I1.sup.2 -I2.sup.2 neccessary for comparison processing must be executed over several processing cycles by a look-up table which performs a computation for squaring the inputs, a subtracter and a memory device for temporarily storing intermediate operational results. Consequently, operations cannot be performed at high speed.
SUMMARY OF THE INVENTION
The present invention has been devised in view of the foregoing drawback of the prior art and an object is to provide an image processing apparatus capable of speeding up processing by enabling execution of operations in a few processing cycles even if the operations between images are complicated.
An image processing apparatus capable of high-speed operations is constructed by providing in parallel a plurality of dyadic look-up tables to which plural items of image data I1, I2 are input as upper order addresses and lower order addresses. The image processing apparatus provides output data f(I1,I2) corresponding to a prescribed function from an address [I1I2]. An arithmetic unit, which executes an operation corresponding to the prescribed function is connected to the output of each of the dyadic look-up tables.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a block diagram illustrating an image processing apparatus according to an embodiment of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
An image processing apparatus in accordance with the invention is equipped with two dyadic look-up tables (D-LUT) 10, 20 each a RAM. The dyadic look-up tables 10, 20 each have a first input IN1 for an upper order address input, a second input IN2 for a lower order address input, and a data output OUT.
Assuming that image data input to the first input IN1 of dyadic look-up table 10 is I1 and data inputted to the second input IN2 is I2, an operational result f.sub.1 (I1,I2) based on a prescribed function f.sub.1 is stored as data at an address [I1I2]. Further, assuming that image data input to the first input IN1 of dyadic look-up table 20 is I1' and data input to the second input IN2 is I2', an operational result f.sub.2 (I1',I2') based on a prescribed function f.sub.2 is stored data at an address [I1'I2'].
When the data I1, I2 are applied to the first an
REFERENCES:
patent: 4709231 (1987-11-01), Sakabara et al.
Kurakake Mitsuo
Muraoka Yutaka
Ootsuka Shouichi
Clark David L.
Fanuc Ltd.
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