Television – Basic receiver with additional function – For display of additional information
Reexamination Certificate
1999-08-23
2002-08-27
Lee, Michael H. (Department: 2714)
Television
Basic receiver with additional function
For display of additional information
C348S581000
Reexamination Certificate
active
06441863
ABSTRACT:
TECHNICAL FIELD
The invention relates to an image processing apparatus and an image processing method which are suitable for use in realization of a picture-in-picture function or a picture-and-picture function and relates to a television receiver or the like having such an image processing circuit.
BACKGROUND ART
In a recent television receiver, a receiver which can perform what is called a picture-in-picture (hereinbelow, referred to as a PinP) to simultaneously display a slave picture plane for an inherent master picture plane or a picture-and-picture (hereinbelow, referred to as a PandP) to simultaneously display two picture planes is being spread. To realize the PinP function or PandP function, an image processing circuit to perform a synchronous crossover or set an image size and a display position is provided in such a kind of television receiver.
The image processing circuit can be constructed by: a field memory; interpolation processing circuits provided at the front and post stages of the field memory; and a memory controller to control the field memory in accordance with the image size and the display position.
That is, in case of reducing the image size, an interpolating process is performed in the interpolation processing circuit at the front stage of the field memory in order to improve a picture quality. An input digital video signal is decimated in accordance with the image size every pixel in the horizontal direction and every line in the vertical direction and the resultant video signal is written into the field memory. The video signal in the field memory is continuously read out.
For example,
FIGS. 1A
to
1
D and
2
show an example in case of reducing an original image of (720 pixels×240 lines) to an image of (360 pixels×120 lines).
As shown in
FIG. 1A
, as an original image, sampling image data D
00
, D
01
, D
02
, D
03
, . . . is inputted in the first one line. In the next (1+1)th line, as shown in
FIG. 1C
, sampling image data D
10
, D
11
, D
12
, D
13
, . . . is inputted.
In this case, in the horizontal direction, as shown in
FIG. 1B
, a write enable signal We is inputted to a field memory every sample and a decimation is performed so as to reduce the number of samples into ½ in the horizontal direction. In the vertical direction, the write enable signal We is inputted every line (refer to
FIGS. 1B and 1D
) and a decimation is performed so as to reduce the number of lines into ½ in the vertical direction.
Thus, the data of each sample is decimated with respect to the horizontal direction and the data of each line is decimated with respect to the vertical direction. As shown in
FIG. 2
, a video signal is written into the field memory in a state where it is reduced into ½.
When the data is continuously read out from the field memory in which the video signal in which the number of samples in the horizontal direction was decimated into ½ and the number of lines in the vertical direction was decimated into ½ as mentioned above has been stored, the original image of (720 pixels×240 lines) can be reduced into the image of (360 pixels×120 lines).
In case of magnifying the image size, the input video signal is continuously written into the field memory. The video signal in the field memory is read out in accordance with the image size and a magnifying process by an interpolation is performed at the post stage of the field memory.
As mentioned above, the image processing circuit can be constructed by the field memory, the interpolation processing circuits provided at the front and post stages of the field memory, and the memory controller. However, if it is intended to realize such an image processing circuit by one field memory, there occurs a problem such that the reading position in the field memory overtakes the writing position and a time-dependent discontinuity occurs.
For example, in case of reducing the image size, as mentioned above, the video signal is written into the field memory while decimating the samples and lines of the input video signal and the data is continuously read out from the field memory. In this case, therefore, an address counter on the reading side is incremented faster than an address counter on the writing side.
That is, now assuming that the video signal is written into the field memory on the basis of a line address count signal on the writing side as shown in
FIG. 3A
, the video signal is read out by a line address count signal as shown in
FIG. 3B
on the reading side. Since the address counter on the reading side is incremented faster than that on the writing side as mentioned above, as shown in
FIG. 3C
, when the synchronous crossover and the size switching are simultaneously performed, an overtake occurs at a point (a) where an address count signal on the reading side and an address count signal on the writing side intersect. Present field data is read out for a period of time (b). Past field data is read out for a period of time (c). Thus, a time-dependent discontinuity occurs.
To solve the above problem, as shown in
FIG. 4
, an apparatus such that two field memories
231
and
232
are provided and the reading and writing operations are alternately performed in the two field memories
231
and
232
every field has been proposed.
In
FIG. 4
, a memory portion
201
is constructed by the two field memories
231
and
232
and two switching circuits
233
and
234
. The writing and reading operations of the two field memories
231
and
232
are switched by the switching circuits
233
and
234
.
The switching circuits
233
and
234
equivalently express processes which are eventually performed by performing writing and reading controls to the two field memories
231
and
232
.
A writing side memory control circuit
204
and a reading side memory control circuit
205
are provided for the memory portion
201
. The writing side memory control circuit
204
controls the field memory serving as a writing side between the field memories
231
and
232
. The reading side memory control circuit
205
controls the field memory serving as a reading side between the field memories
231
and
232
.
A horizontal/vertical interpolation processing circuit
202
performs an interpolating process so as not to cause a deterioration in picture plane when the image size is reduced. That is, when the image size is reduced, the decimating process is performed in the memory portion
201
. If the decimating process is simply performed, however, an aliasing distortion occurs and the picture quality deteriorates. Therefore, the interpolating process is performed in the horizontal/vertical interpolation processing circuit
202
so as not to deteriorate the picture quality. A horizontal/vertical interpolation processing circuit
203
for a magnifying process performs a magnification interpolating process when the image size is magnified. Control information for image processes is supplied to a bus decoder
206
through an internal bus led out from a system controller of the television receiver although not shown. The control information is generated, for example, in accordance with a setting state of a switch or the like on an operation panel of the television receiver.
Image size information (H, VSize) is formed from the bus decoder
206
in accordance with the control information from the system controller. The image size information (H, VSize) is supplied to latch circuits
211
and
212
. The image size information (H, VSize) is inputted to the latch circuits
211
and
212
at a timing of a vertical read clock fvr. Outputs of the latch circuits
211
and
212
are supplied to the writing side memory control circuit
204
and reading side memory control circuit
205
and to a magnification/reduction ratio calculating circuit
207
.
The magnification/reduction ratio calculating circuit
207
forms interpolation processing information according to its aspect ratio on the basis of the image size information (H, VSize). In case of the reducing process, the interpolation pr
Miyazaki Shinichiro
Ohno Takeshi
Shirahama Akira
Frommer William S.
Frommer & Lawrence & Haug LLP
Lee Michael H.
Sony Corporation
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