Image processing apparatus and method of controlling the same

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G06F 1500

Patent

active

055509614

ABSTRACT:
Texture mapping is performed on polygons at the same speed as a polygon drafting process without a texture cache, thereby reducing complexity without an increase in cost. An image memory is constituted in a double-buffer structure, and an address line, a data line and a memory control line are individually connected to each buffer. One of the two buffers is used for texture data, and the other for a drawing result. The texture data is one-dimensional, and the size thereof is less than a maximum value of a column address. The other buffer is an imaginary double buffer with two buffers, one of the buffers being used for reading out image data from a SAM port, the other being used for writing image data produced from polygons. Read/write switching is effected in a vertical flyback period. In the read-out buffer, just after row-directional read-out, the associated row is cleared by the flash write function of a multiport DRAM in a horizontal flyback period, and the next read-out address is output. In synchronism with this, texture data is refreshed.

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Mailloux, Jeff; Speed Memory, Ease Timing Requirements With VRAM Functions; Electronic Design V 37, N 24 p. 95(5); Nov. 23, 1989.
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Nikkei Computer Craphics, Product review "Reality Engine"; G. Kakogawa; Oct. 1992.
Shires, "A New VLSI Graphics Coprocessor--The Intel 82786", IEEE Comuter Graphics And Applications, vol. 6, No. 10, Oct. 1986, New York, pp. 49-55.

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