Image processing apparatus

Image analysis – Histogram processing – For setting a threshold

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364521, 364900, 382 41, G06K 936

Patent

active

048378445

ABSTRACT:
An affine conversion address generated by an affine conversion address generator and a detection signal from an outside-the-image memory area detector are transferred to a first image memory, together with a read signal, via a control bus. Image data is read out from a pixel position of the first image memory designated by the affine conversion address on the address bus of the control bus. The image data read out from the first image memory is supplied to a gate circuit together with the detection signal on the control bus. The gate circuit outputs the image data read out from the first image memory directly or after converting it to predetermined image data in accordance with the detection signal on the control bus. The image data output from the gate circuit is transferred to a second image memory, together with a busy signal indicating a data transfer, via an image bus provided independently of the control bus. Thus, the second image memory stores the transferred image data in accordance with raster addresses sequentially generated in the second image memory itself.

REFERENCES:
patent: 3976982 (1976-08-01), Eiselen
patent: 4052699 (1977-10-01), Micka
patent: 4415928 (1983-11-01), Strolle
patent: 4437121 (1984-03-01), Taylor
patent: 4636783 (1987-01-01), Omachi
patent: 4672680 (1987-06-01), Middleton
patent: 4680630 (1987-07-01), Field
"A New Approach to Image Registration on a Minicomputer", Brad Simpson, 1982, pp. 68-70.

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