Image pickup apparatus with photoelectric conversion...

Television – Camera – system and detail – Solid-state image sensor

Reexamination Certificate

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Details

C348S300000, C348S301000, C348S308000, C348S281000

Reexamination Certificate

active

06734906

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image pickup apparatus for detecting image information of an object, and an image pickup system using the image pickup apparatus.
2. Related Background Art
A CMOS area sensor is one of amplification type sensors, which has a CMOS amplification circuit in each pixel.
The CMOS area sensor is superior to a CCD type area sensor, in terms of random access, a variety of functions and a small power consumption.
A CCD type area sensor has a large power consumption, and photoelectrically converted signals are sequentially transferred to the output circuit so that random access is difficult. A CMOS area sensor can output an image signal by selecting a desired pixel, so that it has a low power consumption and low noises and is easy to be fabricated.
If there is a variation in the characteristics of pixel amplifiers of a CMOS area sensor, it is required to use storage units in order to compensate for the variation. However, if each pixel is provided with a storage unit, a storage unit mount area becomes large and the cost rises. An example of an image pickup apparatus having storage units for compensating for such a variation will be described. A variation in the characteristics of pixel amplifiers can be suppressed by subtracting a noise signal read from the pixel from a pixel signal.
FIGS. 1
to
3
are schematic circuit diagrams showing examples of a conventional variation compensation circuit of an image pickup apparatus. The structure shown in
FIG. 2
is disclosed in JP-A-1-245769, and the structure shown in
FIG. 3
is disclosed in JP-A-9-247546.
Referring to
FIG. 1
, a capacitor CS and a capacitor CN for storing a signal and a noise of each pixel are connected via transistors MS and MN to a vertical output line to which the output terminals of a plurality of pixels are connected. A signal and noise stored in the capacitors CS and CN are transferred to a horizontal output line when transistors MC
1
and MC
2
are turned on by a horizontal shift register (H•SR), and the noise is removed from the signal by a subtraction amplifier.
In the structure shown in
FIG. 2
, the noise is subtracted from the signal by reset means MP
1
and MP
2
connected to the electrodes of capacitors Cp and Cp, and a noise removed signal is temporarily stored in a capacitor CS. In order to remove the noise, while the output electrode side of the capacitor Cp is maintained at a constant potential, the noise is output to the input electrode side of the capacitor Cp, and after the output electrode side of the capacitor Cp is made in a floating state, the signal is input to the input electrode side of the capacitor Cp. Since the input electrode side of the capacitor Cp changes its potential by a (signal−noise) potential and similarly the output electrode side of the capacitor Cp changes its potential by a (signal−noise) potential, a signal with the noise removed can be output. A signal stored in the capacitor CS is transferred to the horizontal output line when the transistor MC is turned on by a horizontal shift register (H•SR).
In the structure shown in
FIG. 3
, the noise read from the vertical output line is subtracted from the signal read from the vertical output line and the noise removed signal is temporarily stored in the capacitor CS. In order to remove the noise, transistors Mt and Mr are turned on and reset, and thereafter during a noise output period, a negative pulse is applied to the capacitor Cp to transfer the charges over the channel potential &phgr;n of the transistor MS to the capacitor CS, which charges are drained by turning on the transistor Mt. Again during the signal output period, a negative pulse is applied to the capacitor Cp to transfer the charges over the channel potential &phgr;s of the transistor MS to the capacitor CS. The charges transferred to the capacitor CS are Cp×(&phgr;s−&phgr;n) which correspond to the noise removed signal.
In such an image pickup apparatus, two capacitors are provided at the minimum at one pixel line (one vertical output line). The capacitance of a capacitor is determined by the thickness of a dielectric layer and the electrode area. The capacitors generally occupy several tens % of the chip area.
In the structure, particularly the structure shown in
FIG. 1
, an amplifier for subtracting the noise from the signal is required for each pixel and the power consumption becomes large. If signals of a plurality of horizontal lines are read at the same time in order to lower a read speed, the temporary storage capacitor is required to have a large capacitance, resulting in a large chip area. In the image pickup apparatus shown in
FIG. 2
, even if the capacitor CS is omitted and the signal and noise are output to the horizontal output line without being temporarily stored, a circuit for subtracting the noise is required for each line, resulting in a large chip area.
A recent digital still camera has several million pixels and an increased consumption power. The number of images capable of being stored therefore reduces and a user is requested to incur a high battery cost.
After the year 2000, an infrastructure of IMT-2000 capable of high speed data communications will be prepared and image communications will prevail. In order to prevail such mobile image communications, a sensor and a peripheral circuit of a low consumption power and a low cost are desired.
SUMMARY OF THE INVENTION
It is an object of the present invention to reduce a chip area.
In order to achieve the above object, according to aspect of the invention, there is provided an image pickup apparatus comprising unit cells arranged in a plurality of lines, each unit cell including a plurality of photoelectric conversion portions arranged at least in a horizontal direction and a common circuit to which signals from the plurality of photoelectric conversion portions are input; and subtracting means shared by respective photoelectric conversion portions of at least one of the unit cells.
According to another aspect of the invention, there is provided an image pickup apparatus comprising: a plurality of photoelectric conversion pixels; and subtracting means shared by at least two photoelectric conversion pixels adjacent in the plurality of photoelectric conversion pixels.
According to another apsect of the invention, there is provided an image pickup apparatus comprising: unit cells arranged in a plurality of lines, each including a plurality of photoelectric conversion portions disposed at least in a horizontal direction and a common circuit to which signals from the plurality of photoelectric conversion portions are input; and signal holding means shared by respective photoelectric conversion portions of at least one of the unit cells.
According to another aspect of the invention, there is provided an image pickup apparatus comprising: a plurality of photoelectric conversion pixels; and signal holding means shared by at least two photoelectric conversion pixels adjacent in the plurality of photoelectric conversion pixels, wherein the signal holding means stores in parallel first and second signals generated in the photoelectric conversion pixel.
The other objects and features of the invention will become more apparent from the following detailed description of preferred embodiments when read in conjunction with the accompanying drawings.


REFERENCES:
patent: 4768085 (1988-08-01), Hashimoto
patent: 4876601 (1989-10-01), Hashimoto et al.
patent: 4910597 (1990-03-01), Harada et al.
patent: 4910599 (1990-03-01), Hashimoto
patent: 4914519 (1990-04-01), Hashimoto et al.
patent: 4942474 (1990-07-01), Akimoto et al.
patent: 4967067 (1990-10-01), Hashimoto et al.
patent: 4985758 (1991-01-01), Hashimoto
patent: 5162912 (1992-11-01), Ueno et al.
patent: 5214272 (1993-05-01), Ueno
patent: 5262850 (1993-11-01), Hashimoto
patent: 5288988 (1994-02-01), Hashimoto et al.
patent: 5315412 (1994-05-01), Mihara et al.
patent: 5424529 (1995-06-01), Hashimoto et al.
patent: 5521640 (1996-05-01), P

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