Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
1997-11-25
2003-09-09
Garber, Wendy R. (Department: 2612)
Television
Camera, system and detail
Solid-state image sensor
C348S295000, C348S312000
Reexamination Certificate
active
06618085
ABSTRACT:
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to an image pickup apparatus for supplying computer equipment with image information.
b) Description of the Related Art
FIG. 1
is a block diagram showing the structure of an image pickup apparatus having a frame transfer type CCD solid state image pickup device.
FIG. 2
is a timing chart illustrating the operation of the same image pickup apparatus.
A CCD solid state image pickup device
1
has an image pickup portion
1
i
, a storage portion
1
s
, a horizontal transfer portion
1
h
and an output portion
1
f
. The image pickup portion
1
i
comprises a plurality of vertical shift registers which are arranged parallel to one another. Respective bits of these vertical shift registers form optical pixels. Such multiple optical pixels of the image pickup portion
1
i
are arranged in the form of a matrix, and information charges are produced on the respective pixels corresponding to the image of an object and independently accumulated in the respective pixels. The storage portion
1
s
comprises a plurality of vertical shift registers, which are connected to the respective vertical shift registers configuring the image pickup portion
1
i
. The number of bits of the respective vertical shift registers of the storage portion
1
s
is set to conform to the number of bits of the vertical shift registers of the image pickup portion
1
i
. The storage portion
1
s
can temporarily store information charges for a single image plane being transferred from the vertical shift registers of the image pickup portion
1
i
. The horizontal transfer portion
1
h
comprises a single horizontal shift register. The respective outputs of the multiple vertical shift registers of the storage portion is are connected to the respective bits of the horizontal shift register. The horizontal shift register sequentially receives information charges which are transferred in one bit units from the multiple vertical shift registers of the storage portion is and transfers them on a line-by-line basis to the output portion
1
f
. The output portion If comprises an electrically independent capacitor and an amplifier, which detects a potential change in the capacitor. The information charges transferred from the horizontal shift register of the horizontal transfer portion
1
h
are received on a pixel-by-pixel basis by the capacitor, and converted into a voltage value. A change in the voltage value is output as an image signal Y
0
(t).
A vertical drive circuit
2
v
produces a polyphase vertical transfer clock &phgr;v in response to a vertical timing signal VT and supplies it to the image pickup portion
1
i
of the solid state image device
1
. The information charges for a single image plane, which are produced and stored on each optical pixel of the image pickup portion
1
i
, are synchronized with the vertical timing signal VT and transferred from the image pickup portion
1
i
to the storage portion
1
s
at high speed. The vertical drive circuit
2
v
produces a polyphase storage clock &phgr;s in response to a horizontal timing signal HT and supplies it to the storage portion
1
s
. The information charges for a single image plane stored in the storage potion
1
s
are transferred on a line-by-line basis to the horizontal transfer portion
1
h
at every cycle of the horizontal timing signal HT. The storage clock &phgr;s also includes a high-speed clock pulse synchronized with the vertical transfer clock &phgr;v for transferring the information charges, which are transferred from the image pickup portion
1
i
at high speed, into the storage portion
1
s
. The vertical drive circuit
2
v
supplies a drain region with a discharge clock &phgr;d, which is started during a vertical scanning period in response to a discharge timing signal DT. The drain region absorbs the electric charges produced excessively in the image pickup portion
1
i
of the solid state image pickup device
1
. The discharge clock &phgr;d controls electric potential in the drain region to discharge the information charges which are stored in the image pickup portion
1
i
. A period L, during which the information charges are completely discharged by the discharge clock &phgr;d and the information charges are started to be transferred by the vertical clock &phgr;v, is an accumulation time of the information charges (i.e., an image pickup period) in the image pickup portion
1
i
. The image pickup period of the solid state image pickup device
1
, namely a shutter speed, can be controlled according to a change in timing of the discharge clock &phgr;d applied to the substrate. Such methods for discharging information charges are disclosed in, for example, Japanese Patent Laid-Open Publication No. Hei 3-22768 and Japanese Patent Laid-Open Publication No. Hei 3-48586.
A horizontal drive circuit
2
h
produces a horizontal transfer clock &phgr;h in response to the horizontal timing signal HT and supplies it to the horizontal transfer portion
1
h
of the solid state image pickup device
1
. Accordingly, the information charges, which are transferred on a line-by-line basis from the storage portion is to the horizontal transfer portion
1
h
, are transferred serially to the output portion
1
f
. The horizontal drive circuit
2
h
produces a reset clock &phgr;r synchronized with the horizontal transfer clock &phgr;h and supplies it to the output portion
1
f
. Thus, information charges stored in the capacitor of the output portion
1
f
are discharged on a pixel-by-pixel basis. In other words, the quantity of electric charges is converted into the voltage value on a pixel-by-pixel basis.
A horizontal timing control circuit
3
h
, which includes a counter for counting a base clock BCK with a given cycle, divides the base clock BCK at a predetermined ratio to produce a horizontal timing signal HT with a horizontal scanning cycle. For example, according to an NTSC method, a base clock BCK having a frequency of 14.32 MHz, which is 4 times larger than a frequency of 3.58 MHz of a color subcarrier used in the signal processing, is divided into 1/910 to produce the horizontal timing signal HT. A vertical timing control circuit
3
v
which includes a counter for counting the horizontal timing signal HT divides the horizontal timing signal at a predetermined ratio to produce a vertical timing signal VT with a vertical scanning cycle. For example, according to the NTSC method, the vertical timing signal VT is produced by further dividing the horizontal timing signal HT, which is the base clock BCK with a frequency of 14.32 MHz divided by 910, by 2/525. Thus, respective timing of the horizontal and vertical scanning of the solid state image pickup device
1
are determined.
An analog signal processing circuit
4
captures the image signal Y
0
(t), which is output from the solid state image pickup device
1
, and produces an image signal Y
1
(t) having a signal processed according to a predetermined format by performing processing such as sample-and-hold, holding and level-compensation. An A/D conversion circuit
5
captures the image signal Y
1
(t) and converts the analog value into digital data on a pixel-by-pixel basis to produce image data D
0
(n). A digital signal processing circuit
6
captures the image data D
0
(n) and performs processing such as color separation or color difference matrix and balance modulation to produce image data D
1
(n) including luminance data and color difference data. The image data D
1
(n) thus produced is sent to a display device such as a TV monitor, or is recorded on a recording medium such as a videodisc.
An exposure control circuit
7
produces a discharge-timing signal. The exposure control circuit
7
integrates the image data D
0
(n) output from the A/D conversion circuit
5
on a pixel-by-pixel basis and changes timing to produce a discharge timing signal DT according to the integrated value. In other words, this discharge timing signal DT is produced with delayed timing if the integrated value with respect to the image data D
0
Garber Wendy R.
Hogan & Hartson LLP
Nguyen Luong
Sanyo Electric Co,. Ltd.
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