Image memory having plural input registers and output registers

Details Image memory having plural input registers and output registers Image memory having plural input registers and output registers

1988-09-02

1990-03-27

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Combined random and sequential addressing

36518912, 36518904, 365 78, 365221, G11C 700, G11C 1140, G11C 1300

Patent

active

049126806

ABSTRACT:
A plurality of registers for writing are connected to data input portions of respective memory devices and a plurality of registers for reading are connected to the data output portions thereof. A random access bus and a serial access bus are respectively connected to both of the registers for writing and the registers for reading. A control circuit controls the memory devices, registers for writing and the registers for reading to effect serial input/output control and random access control.

REFERENCES:
patent: 4639864 (1987-01-01), Ishii
patent: 4796231 (1989-01-01), Pinkham
patent: 4802133 (1989-01-01), Kanuma et al.
National Panasonic, "Digital Integrated Circuits Data", MN4700, Apr. 1987.

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