Computer graphics processing and selective visual display system – Display driving control circuitry – Physically integral with display elements
Patent
1994-07-28
1996-06-25
Hjerpe, Richard
Computer graphics processing and selective visual display system
Display driving control circuitry
Physically integral with display elements
345115, 345185, G07G 500
Patent
active
055304583
ABSTRACT:
An image memory control device is disclosed by which high speed reading processing can be performed without causing a CPU of a computer to have a waiting time and without expanding the system scale. When the CPU tries to perform read access to an image memory, a CPU read mode signal is changed over and a first-in first-out memory controller delivers a read access request to a memory access controller irrespective of presence or absence of read access, and data read in from the image memory are stored into a FIFO memory under the control of the memory controller. Upon read accessing from the computer, the data are transferred from the first-in first-out memory, which assures higher speed operation. Where writing of video data and read/write access of the computer to the image memory are performed by a same system, the FIFO memory is used as a common buffer to them in a time dividing condition by changing over between them.
REFERENCES:
patent: 4642794 (1987-02-01), Lavelle et al.
patent: 5088053 (1992-02-01), Sprague et al.
patent: 5293623 (1994-03-01), Froniewski et al.
Hjerpe Richard
NEC Corporation
Saras Steven J.
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