Image luminance detection and correction employing histograms

Computer graphics processing and selective visual display system – Display driving control circuitry

Reexamination Certificate

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Details

C348S537000

Reexamination Certificate

active

06559837

ABSTRACT:

RELATED APPLICATION(S)
Not Applicable
FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
TECHNICAL FIELD
This invention relates to analog-to-digital conversion of video image frames, and more particularly to employing image luminance histograms to detect the presence of and correct luminance values of a video signal.
BACKGROUND OF THE INVENTION
Presentations using multimedia projection display systems have become popular for conducting sales demonstrations, business meetings, and classroom instruction. In a common mode of operation, multimedia projection display systems receive analog video signals from a personal computer (“PC”). The video signals represent still, partial-, or full-motion display images of the type rendered by the PC. The analog video signals are converted into digital video signals to control digitally-driven display devices, such as a transmissive or reflective liquid crystal displays or digital micro-mirror devices (hereafter “light valves”), to form the display images for projection onto a display screen. A wide variety of such display systems are available from In Focus Systems, Inc., the assignee of this application.
A necessary feature of multimedia display systems is compatibility with the various analog video signal modes and levels generated by PCs and other video sources. The modes typically range from 640×480 to 1600×1200 resolutions provided at image refresh rates ranging from 60 Hz to 100 Hz. The resolution expresses the number of controllable horizontal and vertical pixel elements that can be turned on and off. Given the variety of display modes, multimedia display systems include an interface that attempts to convert the various analog video signal levels and modes to digital video signals suitable for controlling the light valves.
Analog video signals typically include image information (signal levels) for each of the red, green and blue colors, and timing signals, which may include a horizontal synchronizing pulse (“H
SYNC
”) and a vertical synchronizing pulse (“V
SYNC
”), or a composite image and sync signal. The color image information is stored in the PC memory as digital color data and is converted to the analog video signals by digital-to-analog converters. When composite sync is employed, a conventional sync separator is used to extract the H
SYNC
and V
SYNC
timing pulses.
The timing signals synchronize the scanning of the analog video signals across a raster-scanned display device. The H
SYNC
pulse controls the horizontal scanning timing, and the V
SYNC
pulse controls the vertical scanning or video frame refresh timing.
FIG. 1
shows that each video frame
1
typically includes a central active video region
2
surrounded by an inactive or blanked margin
3
. The resolution of a raster-scanned display refers to the number of displayable image information points (“pixels”) in active video region
2
.
Because the light valves employed by multimedia display systems require digital video signals, either the light valve or the display system normally includes an analog-to-digital converter (“ADC”) for converting the PC-generated analog video signals into a digital format suitable for driving the light valve. The ADC is typically digitizes samples of the analog video signal under control of a voltage-controlled oscillator (“VCO”), which is in turn controlled by a phase-locked loop (“PLL”) that locks to a predetermined multiple “n” of the H
SYNC
pulses.
FIG. 2
shows an exemplary analog signal waveform
4
, with plateau regions (pixel data components)
5
that correspond to the color levels of individual pixels in the image display. Consecutive pixel data components
5
are connected by signal transition regions
6
.
FIG. 2
further shows a typical pixel clock waveform
7
, which is generated by the VCO. The number n of pixel clock pulses
8
per H
SYNC
pulse is typically set to match the resolution mode established by the PC or other analog video source. To determine the resolution mode, certain characteristics of the analog video signal, such as the number of H
SYNC
pulses per V
SYNC
pulse, may be used to refer to a mode lookup table. The resulting number n is set to equal the number of pixel data components in each horizontal line of the analog video signal, including those in active video region
2
and blanked margins
3
(FIG.
1
). For example, for a 640×480 screen resolution, n may be set to about 800 to include pixels in blanked regions
3
on either side of the 640 pixel-wide active video region
2
. Thus, pixel clock pulses
8
would cause the ADC to sample analog signal waveform
4
about 800 times along each horizontal scan line of video frame
1
. Unfortunately, n is usually an approximation because it is often difficult to determine the exact proportion of active video region
2
to blanked margin regions
3
(FIG.
1
).
FIG. 2
also shows the desired timing relationship between analog signal waveform
4
and pixel clock waveform
7
. Ideally, the number n of pixel clock pulses
8
is set to establish a one-to-one relationship between pixel clock pulses
8
and pixel data components
5
of analog signal waveform
4
. This one-to-one relationship requires that the pixel clock signal frequency be equal to the analog video signal frequency. Under this relationship, each pixel data component
5
is sampled by a single pixel clock pulse
8
, such that the ADC properly digitizes the instantaneous voltage value of each pixel data component
5
. Because pixel clock pulses
8
have “jitter” zones
9
at their leading and trailing edges, pixel clock pulses
8
should be centered on pixel data components
5
, so that the ADC sampling is not randomly shifted by jitter zones
9
into signal transition regions
6
of analog signal waveform
4
.
The stream of digitized signal values from the ADC form the digital video data signal is conveyed to the light valve to activate or deactivate its pixels in a pattern corresponding to the image defined by analog signal waveform
4
. Unfortunately, such ADC conversion is often imperfect because of sample timing errors caused by pixel clock pulses
8
. Such sample timing errors are typically caused by pixel clock frequency deviations (“tracking” errors) and “phase” errors, both of which may degrade the quality of images generated by the light valve or valves.
FIG. 3
shows a typical tracking error resulting from improperly setting the number n of pixel clocks along the entirety of pixel clock waveform
7
′. As described above, the number n of pixel clock pulses
8
′ should be equal to the number of pixel data components
5
of each horizontal line of analog signal waveform
4
. An improper setting of n results in pixel data components
5
being sampled at inconsistent points. For example, n is set too large in pixel clock waveform
7
′ (i.e. the frequency is too high). The resultant crowding of the pixel clock pulses
8
′ causes an additive leftward drift of pixel clock pulses
8
′ relative to pixel data components
5
. Such drift causes sampling in signal transition regions
6
as shown by positional bracket A in which leading edges
9
′ of the third through sixth of pixel clock pulses
8
′ sample in transition regions
6
of analog signal waveform
4
. Accordingly, the transition region data will be erroneous and the image information from adjacent non-sampled pixel data components
5
will be missing from the digitized video signal. If n is erroneously set large enough, pixel clock pulses
8
′ may be so crowded that individual analog pixel data components
5
may be double-sampled. On the other hand, if n is set too small (i.e. the frequency is too low), the resulting dispersion of pixel clock pulses
8
′ results in a rightward drift in which sampling may also occur in signal transition regions
6
.
To minimize tracking and phase errors, some prior workers have provided some multimedia projection systems with manual controls that permit an operator to adjust the number n and the phase of pixel clocks pulses
8
.

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