Computer graphics processing and selective visual display system – Computer graphics processing – Graphic manipulation
Reexamination Certificate
2000-08-04
2003-07-29
Brier, Jeffery (Department: 2672)
Computer graphics processing and selective visual display system
Computer graphics processing
Graphic manipulation
C382S260000, C348S581000, C708S300000
Reexamination Certificate
active
06600495
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of digital signal processing, and in particular to a digital filter for interpolating and decimating digitally encoded images.
2. Description of Related Art
In a digital display system, sample rate converters (SRCs) are used to effect a scaling of a digitally encoded image. A digitally encoded image, such as a video image, comprises an array of samples of the original image. A display screen area comprises an array of pixels, which may or may not correspond to the array of samples of the original image. If the number of samples in the horizontal and vertical direction are equal to the number of pixels in the horizontal and vertical direction, no scaling is necessary. Each sample is mapped to each corresponding pixel, and the resultant displayed image corresponds to the original image. If there are half the number of pixels as there are samples, every other sample is mapped to a corresponding pixel. The resultant image corresponds to an image that is sampled at half the sampling rate of the original samples. That is, a change of scale is equivalent to a change of sampling rate, hence the term ‘sample rate converter’. Non-integer scaling is effected by generating pixel values corresponding to an estimate of the sample value that would have been obtained had the original sampling rate corresponded to this display scale. If the image is being down-sized, or down-converted, a decimator is used to “remove” sample values; if the image is being up-sized, or up-converted, an interpolator is used to “add” sample values. Conventional display systems include both a vertical sample rate converter and a horizontal sample rate converter to effect the scaling in either or both dimensions. If the display system is configured to only provide down-scaled images, such as a “picture-in-picture” feature, the sample rate converters comprise only a decimator. If the display system is configured to only present up-scaled images, such as a “zoom” feature, the sample rate converters comprise only an interpolator. To provide both up-scaling and down-scaling, the sample rate converters of conventional high-quality display systems include both a decimator and an interpolator.
Decimators and interpolators are typically embodied as digital filters, wherein the resultant pixel value is a weighted average of the samples in the vicinity of the pixel location. The number of samples used to determine the resultant weighted average is termed the number of “taps” of the digital filter. The general equation for an N-tap filter is given by:
y
(
i
+
p
)
=
∑
n
=
0
N
-
1
c
(
n
,
p
)
*
x
(
i
-
n
)
.
(
1
)
where x(i) . . . x(i−(N−1)) are the input samples at each tap of the N-tap filter, p is the phase, and c(n,p) is the weight associated with each input sample at the specified phase. To provide a variety of scale factors, a “polyphase” filter is used. Each phase of a P-polyphase filter corresponds to an integer multiple of 1/P of the output scale for down-sampling, or 1/P of the input scale for up-sampling.
FIG. 1
illustrates a conceptual block diagram of an up-sampling polyphase filter with P phase stages
110
a
-
110
p.
Input samples
101
are provided to each stage. If the output is an up-scaling by a factor of 1:P, the output of each stage
110
a-p
is selected by the switch
120
, and P output values are provided in response to the receipt of each input sample
101
. After producing the P output values, the next input sample
101
is received, and another P outputs are provided. In this manner, P output values are formed for each input sample, thereby providing an up-scaling by a factor of 1:P. If an up-scaling of Q:P is desired, Q of the P stages are selected for output for each input sample. For example, if Q is three, every third stage
101
a,
101
d,
etc. is selected for output for each input sample.
FIG. 2
illustrates a conceptual block diagram of a down-sampling polyphase filter with P phase stages 210
a
-
210
p.
The input samples
201
are provided to select stages via the switch
220
. If the output is a downscaling by a factor of P:1, the output of all P stages
210
a-p
are combined by the adder
230
, and a single output value
231
is provided in response to the receipt of P input samples
201
. After producing the output value, another set of P inputs
201
are used to produce the next output sample
231
. In this manner, one output value is formed for P input samples, thereby providing a downscaling by a factor of P:1. If a downscaling of Q:1 is desired, Q input samples
201
are provided select input stages
210
a-p
and the output of these stages are combined by the adder
230
to produce the single output sample
231
.
A polyphase filter with N taps is typically embodied as a single filter with N registers and a memory that is configured to store the N coefficients for each of the P stages. The appropriate N coefficients are loaded into the N registers of the filter to produce each required output. U.S. Pat. No. 5,892,695, SAMPLE RATE CONVERTER, issued Apr. 6, 1999 for Age J. Van Dalfsen, Jeroen H. J. C. Stessen, and Johannes G. W. M. Janssen, discloses a polyphase filter configuration for effecting up-scaling and down-scaling, and is incorporated by reference herein.
FIG. 3
illustrates an up-scaling polyphase filter as taught in the referenced patent, and
FIG. 4
illustrates a down-scaling polyphase filter as also taught in the referenced patent.
In
FIG. 3
, each input sample x(i)
101
is sequentially clocked into the first polyphase delay elements
310
. For each output sample y
121
, the appropriate coefficient c(n,p(q)) is applied to the multipliers
320
, where p(q) is the phase delay corresponding to the particular phase of the polyphase filter for each output sample y
121
. After each of the upscaled samples y
121
are produced, the next input sample x(i)
101
is clocked into the first polyphase delay element
310
, while the prior x(i) sample is clocked on to the next delay element
311
, and the above process is repeated.
In
FIG. 4
, each input sample x(i)
201
is multiplied by the appropriate coefficient c(n,p(q)), and an intermediate sum is accumulated in the corresponding delay element
410
,
411
, etc. by setting the switches
440
to effect a loop of the contents of the delay element through the adder
430
. When the Q
th
input x(i)
201
arrives in a Q:1 downscaling, the switch
440
is set to effect a transfer of the contents of each delay elements on to the next delay element, also via the adder
430
that adds the appropriate c(n,p(q))*x(i) to the accumulated sum that is transferred to the next delay element. The referenced patent contains additional detail regarding the operation of the filters of
FIGS. 3 and 4
.
The coefficients c(n,p) for each of the P phases of a polyphase filter are typically stored in a local memory, for application to the multipliers
320
,
420
as required. The storage requirement for a P-polyphase filter with N-taps is P*N, and is illustrated by an array
510
of coefficients c(n,p) in FIG.
5
. Each of the P rows of
FIG. 5
contains the N-coefficients for a given phase p, each of the N columns corresponding to each of the coefficients for a given tap.
U.S. Pat. No. 4,866,647 “CONTINUOUSLY VARIABLE DIGITAL DELAY CIRCUIT”, issued Sep. 12, 1989 to C. W. Farrow, incorporated by reference herein, describes a filter, hereinafter a “Farrow filter”, wherein the individual coefficient of each tap is computed based on a polynomial equation. Each column of coefficients
520
is approximated by an L-order polynomial
530
having phase p as the independent variable, and the coefficient c(n,p)
520
at this phase as the dependent variable, using conventional curve fitting techniques. By using a polynomial approximation, the coefficients c(n,p) of any phase value p can be computed, and therefore the Farrow filter provides a continuous phase filter. A continuous phase filter is conventionally termed a continuous
Boland Liza G.
Janssen Johan G.
Brier Jeffery
Gathman Laurie E.
Koninklijke Philips Electronics , N.V.
Yang Ryan
LandOfFree
Image interpolation and decimation using a continuously... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Image interpolation and decimation using a continuously..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Image interpolation and decimation using a continuously... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3014692