Image information decoder with a reduced capacity frame memory

Details Image information decoder with a reduced capacity frame memory Image information decoder with a reduced capacity frame memory

1996-02-29

2000-05-16

Coles, Edward L.

Computer graphics processing and selective visual display system

Display driving control circuitry

Controlling the condition of display elements

345501, 345521, 382232, G06F 1500, G06K 936

Patent

active

060648031

ABSTRACT:
The present invention discloses an MPEG decoder for reproducing moving picture data. A first frame memory (FM0) and a second frame memory (FM1), each of which is composed of 2N slots, are provided. A third frame memory (FM2) is provided which is composed of N+4 slots. Each slot is provided with a memory capacity of eight lines. FM0 and FM1 each have a 1-frame memory capacity for storing reference frames for motion compensation. FM2, on the other hand, has a memory capacity of half a frame+32 lines for B-PICTURE interlace conversion. A slot control memory (SM) is further provided which is composed of 2N+6 words each of which stores a respective slot number of FM2. For an output section to read the slots of FM2 in the correct order, the contents of SM are updated by an control section at the time of the writing of FM2 by a decoding section.

REFERENCES:
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patent: 5197063 (1993-03-01), Nakano et al.
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patent: 5434857 (1995-07-01), Mori
patent: 5598542 (1997-01-01), Leung
patent: 5646693 (1997-07-01), Cismas
Shun-ichi Ishiwata et al., "Development of an MPEG2 decoder LSI-Efficient Memory Allocation", 1994, Proceedings of the 1994 IEICE Spring Conference C-659, Mar. 1994 and an English translation thereof.

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