Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry
Reexamination Certificate
1998-04-23
2002-07-30
Grant, II, Jerome (Department: 2626)
Facsimile and static presentation processing
Facsimile
Specific signal processing circuitry
C358S001100
Reexamination Certificate
active
06426804
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image forming apparatus such as an electrophotographic copying machine, laser printer, facsimile device, etc., and in particular relates to a timing processing technology for an optoelectric conversion element, such as a CCD, etc., and a processing section for processing an image signal read out by the optoelectric conversion element.
2. Description of the Background Art
Many recent image forming apparatuses are constructed to convert reflection light reflected from a manuscript document to an electric signal as image data by using an optoelectric conversion element such as a CCD, etc., and to perform various necessary processings after digitizing the obtained image data in a signal processing section.
At this time, although various timing signals are needed in the CCD and the signal processing section, these signals are generated and supplied by an external timing circuit. In such background art, a drive signal for driving the CCD and a timing signal supplied to a signal processing section are created by a timing generating circuit constructed with parts of random logic, a delay line, an exclusively used IC, etc. per each of respective CCDs. As a result, a timing time and delay time have been fixed.
The above matter is concretely described hereinafter.
FIG. 12
is a block diagram of a reading-out section of an electrophotographic copying machine (hereinafter referred to as a “copying machine”) shown as an example of a background image forming apparatus. Since the overall operation and function thereof are already well known, the functional portion related to the subject matter to be solved in the present invention is described, referring to
FIGS. 13 and 14
showing timing waveforms of a main part of a reading out section.
A timing generating section
103
as shown in this example is constructed with a timing generator
103
a,
an exclusively used IC
103
b,
and a random logic and delay line
103
c.
The timing generating section
103
supplies a timing signal to CCD
1
in a main part of a reading out system and a signal processing section
2
, etc. The signal processing section
2
has functions of processing an image data signal and converting the image data signal to digital data.
Two types of phase-shifted shift clock gate signals (&phgr;
11
, &phgr;
12
, &phgr;
21
, &phgr;
22
) are supplied to adjacent cells of the CCD
1
from the timing generating section
103
. The output from the CCD is coordinated by two systems of buffer circuits
2
a
-
1
and
2
a
-
2
. An offset clamp (CLMP) gate signal is applied to analog multiplexers
2
b
-
1
and
2
b
-
2
from the timing generating section
103
, and thereby the CCD
1
transmits only a cell signal intended at respective timings to subsequent stage(s).
The signal from the CCD
1
is further coordinated by buffer circuits
2
c
-
1
,
2
c
-
2
, and the signals thus coordinated are transmitted to sample and hold (S & H) circuits
2
d
-
1
and
2
d
-
2
to which sample clock signals (SHCK
1
and SHCK
2
) are supplied from the timing generating section
103
. Next, the signal from the CCD
1
is further transmitted to automatic gain control (GCA) circuits
2
e
-
1
and
2
e
-
2
.
Furthermore, a multiplex (MPX) gate signal is applied to a multiplex (MPX) circuit
2
f,
and thereby the two types of signals are unified into one signal, and the signal thus unified is applied to an AD conversion circuit (A/D converter)
2
g.
In the AD conversion circuit
2
g,
the signal is converted from an analog signal to a digital signal on the basis of an AD converter gate signal (ADCK) applied to the AD conversion circuit
2
g.
Thereafter, digital image data corresponding to the image on the manuscript document is output by a latch (LATCH) circuit
2
h,
to which a latch clock (LH) gate signal is applied.
However, as mentioned heretofore, regarding the driving signal for use in the CCD
1
or the timing signal for the respective processing blocks in the signal processing section
2
, the timing generator
103
generates the various timing signals such as SHCK
1
, SHCK
2
, MPX, ADCK, LH, etc. as shown in
FIGS. 12-14
. That is, since such various timing signals have been generated by the background apparatus employing random logic, a delay line, or other parts such as an exclusively used IC per each of respective CCDs, the timing time and the delay time are set and fixed so as to fit those times to the CCD
1
.
For this reason, in a case that the CCD
1
has to be replaced, it has been necessary to replace also the exclusively used IC
103
b
for generating the timing signals corresponding to the replaced CCD. Furthermore, since the timing of the image data processings varies very often due to replacing the CCD
1
and the exclusively used IC
103
b,
it has been necessary to change also the timing time and the delay time of the timing signals supplied to the signal processing section
103
on such an occasion.
As a result, even though a CCD has been rendered comparatively low-cost in recent years and can be procured easily, designing of circumferential apparatuses has to be practiced once again as the CCD
1
and the exclusively used IC
103
b
have to be replaced together, and thereby costs increase.
Furthermore, since the delay of the image data processing between the respective signal processing blocks is largely influenced by a value of voltages applied to the respective circuit blocks and ambient temperature, if image data are processed with high speed by use of timing signals supplied from an external timing generating circuit, a very small shift of the timing can cause very serious problems. Thereby, when image processing has to be performed with high quality, the accuracy of timings required to the timing generating section
103
turn out to be very strict and quick action for coping with problems may become very difficult. Even though such quick action can be realized, such an apparatus which can realize such quick action then turns out to be very expensive.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above-mentioned problems in order to improve such various subject matter.
It is accordingly one object of the present invention to solve and improve the above-mentioned drawbacks in the background art.
It is another object of the present invention to provide a novel image forming apparatus capable of solving and improving the above-mentioned drawbacks in the background art.
It is still another object of the present invention to provide a novel image forming apparatus capable of making unnecessary any new designing at a time of replacing a CCD, etc., by constructing a timing generating unit without employing any exclusively used IC.
It is still another object of the present invention to provide a novel image forming apparatus capable of easily replacing a CCD without resulting in any unnecessary cost increases.
It is still another object of the present invention to provide a novel image forming apparatus capable of accomplishing image data processing with low-cost and at high speed by delaying a timing signal corresponding to a delay time between an input image signal and an output image signal per each of respective processing circuits, and for processing image data in such a state.
REFERENCES:
patent: 4532541 (1985-07-01), Cooper
patent: 5191434 (1993-03-01), Kim
patent: 5461487 (1995-10-01), Askura
patent: 5655048 (1997-08-01), Ueda
patent: 5706387 (1998-01-01), Makisshima
patent: 5929899 (1999-07-01), Takahashi
patent: 6104864 (2000-08-01), Kondo et al.
patent: 6256063 (2001-07-01), Saito
Inage Osamu
Kanno Tooru
Grant II Jerome
Ricoh & Company, Ltd.
Worku Negussie
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