Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2006-10-24
2006-10-24
Shalwala, Bipin (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S600000, C345S690000, C345S099000
Reexamination Certificate
active
07126572
ABSTRACT:
A display panel13having a plurality of pixels14each divided into P (P=3) sub-pixels15a,15band15c,and a source driver12for driving each pixel14in accordance with three J (=8)-bit data values corresponding to the sub-pixels15a,15b,and15c,and a signal processing circuit12for distributing K(=12)-bit (K>J) input image data as M (M=6) time-shared frame data values and supplying the frame data values to the source driver12are arranged. 2K−J(=16) gray levels insufficient due to the difference between the numbers of bits of K-bit input image data and J-bit driving signals of the source driver12is realized by combinations of time-shared frame data of (P×M=18) ways performed for the sub-pixels15a,15b,and15cin accordance with the M time-shared frame data values.
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Koga Koichi
Okuzono Noboru
Yamaguchi Machihiko
Lewis David L.
McGinn IP Law Group PLLC
NEC LCD Technologies Ltd.
Shalwala Bipin
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