Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-07-01
2002-10-15
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S204000
Reexamination Certificate
active
06466193
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image display device and method for displaying images by sequentially sampling image signals being inputted for a display screen having an aspect ratio of X:Y.
2. Description of the Related Art
Display devices typified by liquid crystal display devices have advantages in being thin, lightweight, and having lower power consumption. By making use of, these features, they are used as display devices for personal computers and word processors and as display devices for TVs and car navigation systems. Furthermore, they are used as projection displays. In this way, they are used in various applications. Among. others, active matrix liquid crystal display devices (AMLCDS) including display screens having display pixels arranged in rows and columns, each of which pixel is electrically connected with switching elements, can realize good image quality without crosstalk between adjacent pixels. Because of these features, active matrix liquid crystal display devices are being earnestly investigated and developed. In recent years, the aspect ratio of the display screen has shifted from 4:3 to 16:9 at which the image is elongated in the direction of horizontal scanning and which permits visual perception of a large-sized screen.
Where an image signal such as a TV signal having information about 4:3 aspect ratio picture is displayed on a liquid crystal display device having a display screen with an aspect ratio of 16:9, it is common practice to sample a previously image-processed picture signal at successive points by an image-processing technique using a frame memory or the like, and then the image is displayed.
FIG. 4
is a block diagram schematically showing the configuration of the prior art image display device. For example, this device has an input processing circuit
1
that is composed of a demodulator circuit
103
, a matrix circuit
104
, and an analog-to-digital converter circuit
105
as shown in FIG.
5
. An image signal is applied via input terminals
101
and
102
and demodulated into brightness signals Y
1
, Y
2
, chrominance signals C
1
, C
2
, and synchronizing signals S
1
, S
2
by the demodulator circuit
103
. Then, the matrix circuit
104
demodulates three primary signals R
1
, G
1
, B
1
; R
2
, G
2
, and B
2
from the brightness signals Y
1
, Y
2
and the chrominance signals C
1
, C
2
. The three primary color signals R
1
, G
1
, B
1
; R
2
, G
2
, B
2
and synchronizing signals S
1
, S
2
are applied to the A/D converter circuit
105
, which converts the input signals into digital form, or image signals VD
1
and VD
2
. These image signals VD
1
and VD
2
are supplied to a frame synchronizer circuit
2
shown in FIG.
1
.
As shown in
FIG. 6
, the frame synchronizer circuit
2
consists of a control circuit
201
and a frame memory
202
. The control circuit
201
controls reading and writing of the image signal VD
2
to and from the frame memory
202
in response to the synchronizing signals S
1
and S
2
supplied to the control circuit
201
. The image signals VD
1
and VD
2
, which are synchronized to each other on frame period, are supplied to a data converter circuit
3
shown in FIG.
4
.
The data converter circuit
3
converts data about the image signals VD
1
, VD
2
into data adapted for image display on the liquid crystal display device
7
and sends the data to an image synthesizer circuit
5
. A remaining area signal generator circuit
4
produces a remaining area signal that is supplied to the liquid crystal display device
7
except for the effective image display period for the liquid crystal display device
7
. The image synthesizer circuit
5
produces a combination of the remaining area signal and an image signal produced from the data converter circuit
3
. The synthesized image signal from the image synthesizer circuit
5
is sent to an output processing circuit
6
. This output processing circuit
6
performs various kinds of processing, such as digital-to-analog conversion, gamma correction, and polarity switching, to convert the signal to a signal adapted for the liquid crystal display device
7
.
As shown in
FIG. 7
, the liquid crystal display device
7
comprises a liquid crystal panel
701
, four X-driver circuits
703
-
1
,
703
-
2
,
703
-
3
,
703
-
4
electrically connected with the liquid crystal panel
701
, a Y-driver circuit
704
for supplying scanning pulses for display panel, and a control circuit portion
705
. The four X-driver circuits
703
-
1
,
703
-
2
,
703
-
3
, and
703
-
4
sample an image signal to thereby supply a desired voltage for display panel.
Although not illustrated in the figure, the liquid crystal panel
701
has a layer of a twisted-nematic liquid crystal sandwiched between an array substrate and a counter substrate via orientation films. A sealing material makes these components stationary relative to each other. Polarizing plates are mounted on the outer surfaces of the substrates such that their axes of polarization are mutually perpendicular to each other. As an example, 320×3 signal lines Xi (i=1, 2, . . . , 960) and 240 scanning lines Yj (j=1, 2, . . . , 240) are arranged to extend perpendicularly to each other. Pixel electrodes consisting of indium-tin oxide (ITO) are arranged near the intersections of the signal lines Xi and scanning lines Yj via inverted-staggered thin-film transistors (TFTs). These TFTs comprise a thin film of amorphous silicon as an active layer. Auxiliary capacitor lines Cj (j=1, 2, . . . , 240) extending parallel to the scanning lines Yj are arranged on the array substrate. These auxiliary capacitor lines have regions overlapping with the pixel electrodes. The pixel electrodes and the auxiliary capacitor lines Cj form auxiliary capacitors (CS) at the pixels.
The counter substrate has layers of color filters (not shown) of three primary colors red (R), green (G), and blue (B) that are positioned between matrix light-shielding layers (not shown) to achieve color display. One of the light-shielding layers acts to shield gaps among the TFTs formed on the array substrate, the signal lines Xi, and the pixel electrodes. The other light-shielding layer serves to shield the gaps between the scanning lines Yj and the pixel electrodes. Furthermore, a counter electrode consisting of ITO as described above is located on the counter substrate.
The control circuit portion
705
of the liquid crystal panel
701
supplies a horizontal clock signal (XCK), a horizontal start signal (XST), and image signals to the X-driver circuits
703
-
1
,
703
-
2
,
703
-
3
, and
703
-
4
and produces a vertical clock signal YCK and a vertical start signal YST to the Y-driver circuit
704
.
One example of the data converter circuit
8
is shown in FIG.
8
. One form of display provided by the liquid crystal display device
7
is shown in
FIGS. 9A-9D
. The structure of the data converter circuit
8
is described in detail by referring to FIGS.
8
and
9
A-
9
D. The data converter circuit
8
comprises
1
H memory circuits
301
,
302
,
310
, writing control circuits
303
,
311
, reading control circuits
304
,
312
, selector circuits
305
,
306
,
307
,
308
, and a digital filter
309
.
It is assumed that the liquid crystal display device
701
uses a display screen
702
with an aspect ratio of 16:9 as shown in FIG.
9
A. The selector circuit
307
of the data conversion circuit
3
supplies that of the image signals VD
1
and VD
2
selected by the selector circuit
306
to the image synthesizer circuit
5
. The image signal supplied in this way is displayed on the viewing screen with an aspect ratio of 16:9 during an effective display period that is 80% of the horizontal scanning period of 1 H. In consequence, a display in the form shown in
FIG. 9A
is provided.
Then, the display screen
702
is divided into display areas A and B with an aspect ratio of 9:8 as shown in FIG.
9
B. Image signals are displayed on these display areas. In response to the input synchronizing signal S
1
a
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Said Mansour M.
Shalwala Bipin
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