Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-10-06
2001-12-25
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S690000, C345S090000
Reexamination Certificate
active
06333727
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image display device and an image display method for displaying an image on a screen.
2. Description of the Related Art
CRTs (cathode ray tubes) have been used for many years as display devices for computers. CRTs are still widely used because they are inexpensive. However, a CRT requires a large area for installation and is likely to have image distortion. Moreover, it is difficult to reduce its power consumption. In contrast, an LCD (liquid crystal display) does not require a large area for installation, and is not likely to have image distortion. Moreover, it is relatively easy to reduce LCD power consumption. Therefore, LCDs are expected to replace CRTs in the future.
In order to drive an LCD device, an LCD image signal can be input to the LCD device directly from a computer, or a CRT image signal output from a computer can be converted into an LCD image signal and input to the LCD device.
FIG. 5
illustrates a conventional device for converting a CRT image signal into an LCD image signal. The device includes an image amplifier
10
for amplifying a CRT image signal “a” and outputting an amplified image signal “b”, an A/D converter
11
for performing an A/D conversion for the image signal “b” and outputting image data “c”, and a memory
12
having a capacity sufficient for storing at least one frame (corresponding to one screen) of image data “c”. The device further includes a memory controller
13
for controlling write and read operations of the memory
12
, and an LCD controller
14
for converting image data “d” output from the memory
12
into an LCD image signal “e” and outputting the LCD image signal “e”.
The image amplifier
10
shapes the waveform of the analog CRT image signal “a” and outputs the resulting image signal “b” to the A/D converter
11
. The A/D converter
11
converts the image signal “b” into the digital image data “c” so that the signal can be easily handled by an LCD device, and outputs the image data “c” to the memory
12
. The memory controller
13
receives the CRT image signal “a” through a path (not shown). The memory controller
13
produces, using a PLL (phase locked loop) circuit provided therein, a write control signal “f” which is in synchronization with a synchronization signal of the image signal “a”, and outputs the write control signal “f” to the memory
12
. The memory controller
13
also produces a read control signal “g” which is in synchronization with a clock signal (generated by a reference clock circuit provided in the memory controller
13
) and outputs the read control signal “g” to the memory
12
. The memory
12
successively receives and stores the image data “c” from the A/D converter
11
in synchronization with the write control signal “f”, and successively outputs the image data “d” to the LCD controller
14
in synchronization with the read control signal “g”. The LCD controller
14
converts the image data “d” into the image signal “e” which is more suitable for driving the LCD device, and outputs the image signal “e” to the LCD device.
As described above, the memory controller
13
generates the write control signal “f ” in synchronization with the synchronization signal of the image signal “a”, and generates the read control signal “g” in synchronization with the clock signal generated in the memory controller
13
. Therefore, the write control signal “f” and the read control signal “g” are not in synchronization with each other, and the write operation of the image data “c” and the read operation of the image data “d” are not in synchronization with each other. This is because the synchronization timing of the CRT image signal “a” varies depending upon the resolution of the CRT, whereby the synchronization timing of the image data “c” (which is obtained through an A/D conversion of the image signal “a”), may not match the synchronization timing of the LCD image data “d”. Thus, it is required that the memory
12
functions as a buffer, and that the memory controller
13
is provided along with the memory
12
. If the synchronization timing of the CRT image signal “a” matches the synchronization timing of the LCD image signal “e”, then, the memory
12
and the memory controller
13
are optional.
However, if noise is included in the image signal “a” input to the image amplifier
10
in the device illustrated in
FIG. 5
, the noise is also converted by the A/D converter
11
and by the LCD controller
14
. In such a case, the LCD image signal “e” includes the noise, which disturbs the display of the LCD device.
Referring to
FIG. 6
, consider a situation where frames
21
,
22
, . . . ,
26
are to be successively displayed, wherein a certain pixel
27
at one screen position is supposed to maintain a gray-scale level value of 50 throughout the. frames
21
to
26
. If noise is included in the image signal “a”, the gray-scale level for the pixel
27
may vary from 50 to 49, 50, 50, 51 and 50 for the frames
21
to
26
, respectively. Accordingly, binary pixel data representing the gray-scale level of the pixel
27
(included in the digitized image data “c” from the A/D converter
11
) may vary from 110010 to 110001, 110010, 110010, 110011 and 110010.
The degree of the variation in the pixel data included in the digitized image data “c” is dependent upon the level of the noise included in the CRT image signal “a”, and it may be insignificant. In fact, in a display method where the entire image data is updated after each frame, such variation is often imperceptible to human eyes. In a display method where one image is displayed by using a plurality of frames, however, the variation in the pixel data may be distributed to the plurality of frames. In other words, when the number of gray-scale levels represented by an analog image signal “a” cannot be represented by a single frame of image data “e”, so that a number of frames of image data “e” are used to represent the number of gray-scale levels, the variation in the pixel data may be distributed to the number of frames.
For example, referring to
FIG. 7
, assume that the number of gray-scale levels of one pixel which can be represented by the analog image signal “a” is 4, while the number of gray-scale levels which can be represented by the digitized pixel data is 2. In such a case, three frames are used to represent the gray-scale level for the pixel. When the gray-scale level of the pixel represented by the analog image signal “a” is 0, the gray-scale level is set to 0 throughout the three frames. When the gray-scale level of the pixel represented by the analog image signal “a” is 1, the gray-scale level is set to 1 for one of the three frames, and 0 for the other two frames.
Referring to a timing diagram illustrated in
FIG. 8A
, when the gray-scale level of a pixel represented by the analog image signal “a” is 0, the gray-scale level of the pixel is set to 0 for all of a set of three frames by the pixel data included in the image data “e”. When the gray-scale level of a pixel represented by the analog image signal “a” is 1, the gray-scale level of the pixel is set to 1 for the first one of the three frames, and 0 for the following two frames.
FIG. 8B
illustrates a timing diagram, similar to that illustrated in FIG. BA, in a situation where the gray-scale level of the pixel represented by the image signal “a” is supposed to be 1 throughout the illustrated frames, but the gray-scale level varies to 0 or 2 due to noise included in the image signal “a”. In such a case, although the first set of three frames may appropriately represent the gray-scale level of 1, the second three frames may represent the gray-scale level of 0, and the third three frames may represent the gray-scale level of 2, as illustrated in FIG.
8
B. Thus, the gray-scale level of the pixel may fluctuate.
Particularly, when the display device is used in a computer, on which a static image is often displayed, the noise included in the image signal “a” may result in a flicker on the display screen, which is li
Kovalick Vincent E.
Nixon & Vanderhye PC
Shalwala Bipin
Sharp Kabushiki Kaisha
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